參數(shù)資料
型號(hào)： EP7311-IR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 31/42頁(yè)
文件大?。?/td> 0K
描述： IC ARM720T MCU 74MHZ 204-TFBGA
標(biāo)準(zhǔn)包裝： 119
系列： EP7
核心處理器： ARM7
芯體尺寸： 32-位
速度： 74MHz
連通性： 編解碼器，EBI/EMI，IrDA，鍵盤，多媒體編解碼器，SPI/Microwire1，UART/USART
外圍設(shè)備： LCD，LED，MaverickKey，PWM
輸入/輸出數(shù)： 27
程序存儲(chǔ)器類型： ROMless
RAM 容量： 56K x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 2.7 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 204-TFBGA
包裝： 托盤
其它名稱： 598-1228
37
4341H–MP3–10/07
AT8xC51SND2C/MP3B
9.
Interrupt System
The AT8xC51SND2C, like other control-oriented computer architectures, employ a program
interrupt method. This operation branches to a subroutine and performs some service in
response to the interrupt. When the subroutine completes, execution resumes at the point where
the interrupt occurred. Interrupts may occur as a result of internal AT8xC51SND2C activity (e.g.,
timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., key-
board). In all cases, interrupt operation is programmed by the system designer, who determines
priority of interrupt service relative to normal code execution and other interrupt service routines.
All of the interrupt sources are enabled or disabled by the system designer and may be manipu-
lated dynamically.
A typical interrupt event chain occurs as follows:
An internal or external device initiates an interrupt-request signal. The AT8xC51SND2C,
latches this event into a flag buffer.
The priority of the flag is compared to the priority of other interrupts by the interrupt handler.
A high priority causes the handler to set an interrupt flag.
This signals the instruction execution unit to execute a context switch. This context switch
breaks the current flow of instruction sequences. The execution unit completes the current
instruction prior to a save of the program counter (PC) and reloads the PC with the start
address of a software service routine.
The software service routine executes assigned tasks and as a final activity performs a RETI
(return from interrupt) instruction. This instruction signals completion of the interrupt, resets
the interrupt-in-progress priority and reloads the program counter. Program operation then
continues from the original point of interruption.
Table 9-1.
Interrupt System Signals
Six interrupt registers are used to control the interrupt system. 2 8-bit registers are used to
enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 9-4 and Table 9-5).
Four 8-bit registers are used to establish the priority level of the different sources: IPH0, IPL0,
IPH1 and IPL1 registers (see Table 9-6 to Table 9-9).
9.1
Interrupt System Priorities
Each of the interrupt sources on the AT8xC51SND2C can be individually programmed to one of
four priority levels. This is accomplished by one bit in the Interrupt Priority High registers (IPH0
and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and IPL1). This provides each
interrupt source four possible priority levels according to Table 9-2.
Signal
Name
Type
Description
Alternate
Function
INT0
I
External Interrupt 0
P3.2
INT1
I
External Interrupt 1
P3.3
KIN0
I
Keyboard Interrupt Input
See section “Keyboard Interface”, page 204.
-
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