參數(shù)資料
型號(hào)： EP4SGX70HF35I3
廠商： Altera
文件頁(yè)數(shù)： 68/82頁(yè)
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 70K 1152FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 2904
邏輯元件/單元數(shù)： 72600
RAM 位總計(jì)： 7564880
輸入/輸出數(shù)： 488
電源電壓： 0.87 V ~ 0.93 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1152-BBGA
供應(yīng)商設(shè)備封裝： 1152-FBGA（27x27）
1–62
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
I/O Timing
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
Figure 1–7 shows the timing diagram for the oe and dyn_term_ctrl signals.
Duty Cycle Distortion (DCD) Specifications
Table 1–51 lists the worst-case DCD for Stratix IV devices.
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O Timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
f The Excel-based I/O Timing spreadsheet is downloadable from the Literature:
Figure 1–7. Timing Diagram for the oe and dyn_term_ctrl Signals
Table 1–51. Worst-Case DCD on Stratix IV I/O Pins (1)
Symbol
–2/–2×
Speed Grade
–3
Speed Grade
–4
Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
Note to Table 1–51:
(1) The listed specification is only applicable to the output buffer across different I/O standards.
dyn_term_ctrl
oe
RX
Tristate
TX
TRS_RT
TRS_RT
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EP4SGX70HF35I3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 2904 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX70HF35I4 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 2904 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX70HF35I4N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV GX 2904 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4-SI 制造商:Box Enclosures & Assembly Services 功能描述:END PLATE FOR SERIES 4, SILVER ANODIZED, 2.11 H X 6.68 W 制造商:Box Enclosures & Assembly Services 功能描述:Enclosure End Plate 制造商:Box Enclosures & Assembly Services 功能描述:END PLATE; Accessory Type:End Plate; For Use With:Extruded Aluminum Enclosures, BEX Series 4; Body Color:Silver; Body Material:Aluminum; External Height:2.11"; External Width:6.68"; Features:Silver; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
EP4-SPR-BULK 功能描述:SONIC DEFENDER SMALL CLEAR RoHS:是 類(lèi)別:音頻產(chǎn)品 >> 配件 系列:EarPro 標(biāo)準(zhǔn)包裝:1 系列:- 附件類(lèi)型:墊圈 材質(zhì):氯丁橡膠 顏色:黑 適用于相關(guān)產(chǎn)品:Sonalert? 信號(hào)設(shè)備 其它名稱:458-1048
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