參數(shù)資料
型號(hào): EP4CGX30CF23I7N
廠商: Altera
文件頁數(shù): 9/42頁
文件大?。?/td> 0K
描述: IC CYCLONE IV GX FPGA 30K 484FBG
產(chǎn)品培訓(xùn)模塊: Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝: 60
系列: CYCLONE® IV GX
LAB/CLB數(shù): 1840
邏輯元件/單元數(shù): 29440
RAM 位總計(jì): 1105920
輸入/輸出數(shù): 290
電源電壓: 1.16 V ~ 1.24 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FBGA(23x23)
Chapter 1: Cyclone IV Device Datasheet
1–17
Switching Characteristics
December 2013
Altera Corporation
Transceiver Performance Specifications
Table 1–21 lists the Cyclone IV GX transceiver specifications.
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4)
Symbol/
Description
Conditions
C6
C7, I7
C8
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL
Input frequency
from REFCLK input
pins
50
156.25
50
156.25
50
156.25
MHz
Spread-spectrum
modulating clock
frequency
Physical interface
for PCI Express
(PIPE) mode
30
33
30
33
30
33
kHz
Spread-spectrum
downspread
PIPE mode
0 to
–0.5%
——
0 to
–0.5%
——
0 to
–0.5%
——
Peak-to-peak
differential input
voltage
0.1
1.6
0.1
1.6
0.1
1.6
V
VICM (AC coupled)
1100 ± 5%
mV
VICM (DC coupled)
HCSL I/O
standard for PCIe
reference clock
250
550
250
550
250
550
mV
Transmitter REFCLK
Phase Noise (1)
Frequency offset
= 1MHz – 8MHZ
——
–123
–123
–123
dBc/Hz
Transmitter REFCLK
Total Jitter (1)
42.3
42.3
42.3
ps
Rref
——
2000
± 1%
——
2000
± 1%
——
2000
± 1%
Transceiver Clock
cal_blk_clk
clock
frequency
10
125
10
125
10
125
MHz
fixedclk
clock
frequency
PCIe Receiver
Detect
125
125
125
MHz
reconfig_clk
clock frequency
Dynamic
reconfiguration
clock frequency
2.5/
37.5
—50
2.5/
37.5
—50
37.5
—50
MHz
Delta time between
reconfig_clk
——
2
2
2
ms
Transceiver block
minimum
power-down pulse
width
——
1
1
1
s
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