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參數(shù)資料
| 型號： | EP4CE10F17I7N |
| 廠商： | Altera |
| 文件頁數(shù)： | 35/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CYCLONE IV FPGA 10K 256FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色產(chǎn)品： | Cyclone? IV FPGAs |
| 標準包裝： | 90 |
| 系列： | CYCLONE® IV E |
| LAB/CLB數(shù)： | 645 |
| 邏輯元件/單元數(shù)： | 10320 |
| RAM 位總計： | 423936 |
| 輸入/輸出數(shù)： | 179 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-FBGA（17x17） |
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Chapter 1: Cyclone IV Device Datasheet
Glossary
December 2013
Altera Corporation
T
tC
High-speed receiver and transmitter input and output clock period.
Channel-to-
channel-skew
(TCCS)
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin
Delay from the clock pad to the I/O input register.
tCO
Delay from the clock pad to the I/O output.
tcout
Delay from the clock pad to the I/O output register.
tDUTY
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
tFALL
Signal high-to-low transition time (80–20%).
tH
Input register hold time.
Timing Unit
Interval (TUI)
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
Period jitter on the PLL clock input.
tOUTJITTER_DEDCLK
Period jitter on the dedicated clock output driven by a PLL.
tOUTJITTER_IO
Period jitter on the general purpose I/O driven by a PLL.
tpllcin
Delay from the PLL inclk pad to the I/O input register.
tpllcout
Delay from the PLL inclk pad to the I/O output register.
Transmitter
Output
Waveform
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
tRISE
Signal low-to-high transition time (20–80%).
tSU
Input register setup time.
U
——
Table 1–46. Glossary (Part 4 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
OH
Negative Channel (n) = V
OL
Ground
VOD
V
OD
V
OD
0 V
Vos
p
- n
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4CE10F17I8L | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE10F17I8LN | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE10F23C8N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CE10F23I7N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CE10U14I7N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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