
Altera Corporation
7–41
October 2007
Stratix II GX Device Handbook, Volume 2
PLLs in Stratix II and Stratix II GX Devices
Software Support
Table 7–15 summarizes the signals used for clock switchover.
All the switchover ports shown in
Table 7–15 are supported in the
altpll
megafunction in the Quartus II software. The altpll
megafunction supports two methods for clock switchover:
■
When selecting an enhanced PLL, you can enable both the automatic
and the manual switchover, making all the clock switchover ports
available.
■
When selecting a fast PLL, you can use only enable the manual clock
switchover option to select between inclk0 or inclk1. The
clkloss
, activeclock and the clkbad0, and clkbad1 signals
are not available when manual switchover is selected.
If the primary and secondary clock frequencies are different, the
Quartus II software selects the proper parameters to keep the VCO within
the recommended frequency range.
Table 7–15. altpll Megafunction Clock Switchover Signals
Port
Description
Source
Destination
inclk0
Reference clk0 to the PLL.
I/O pin
Clock switchover circuit
inclk1
Reference clk1 to the PLL.
I/O pin
Clock switchover circuit
Signal indicating that inclk0 is no longer
toggling.
Clock switchover
circuit
Logic array
Signal indicating that inclk1 is no longer
toggling.
Clock switchover
circuit
Logic array
clkswitch
Switchover signal used to initiate clock
switchover asynchronously. When used in
manual switchover, clkswitch is used as a
select signal between inclk0 and inclk1
clswitch = 0 inclk0
is selected
and vice versa.
Logic array or I/O pin
Clock switchover circuit
Signal indicating that the switchover
circuit detected a switch condition.
Clock switchover
circuit
Logic array
locked
Signal indicating that the PLL has lost
lock.
PLL
Clock switchover circuit
Signal to indicate which clock (0 =
inclk0
, 1= inclk1) is driving the PLL.
PLL
Logic array
(1)
These ports are only available for enhanced PLLs and in auto mode and when using automatic switchover.