參數(shù)資料
型號(hào): EP20K600EBC652-3
廠商: Altera
文件頁數(shù): 43/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 600K 652-BGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 12
系列: APEX-20K®
LAB/CLB數(shù): 2432
邏輯元件/單元數(shù): 24320
RAM 位總計(jì): 311296
輸入/輸出數(shù): 488
門數(shù): 1537000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 652-BGA
供應(yīng)商設(shè)備封裝: 652-BGA(45x45)
Altera Corporation
31
APEX 20K Programmable Logic Device Family Data Sheet
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in Figure 19.
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
ESB
to System Logic
Address Decoder
Port A
Port B
address_a[]
address_b[]
data_a[]
data_b[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
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EP20K600EBC652-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K600EBI652-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K600EBI652-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K600EBI652-2X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 2432 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K600EBI652-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA