參數(shù)資料
型號: EP20K30EFI324-1ES
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 29/114頁
文件大?。?/td> 1623K
代理商: EP20K30EFI324-1ES
Altera Corporation
21
APEX 20K Programmable Logic Device Family Data Sheet
Figure 9. APEX 20K Interconnect Structure
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10 shows how the FastTrack Interconnect uses the local
interconnect to drive LEs within MegaLAB structures.
MegaLAB
I/O
MegaLAB
I/O
MegaLAB
I/O
Column
Interconnect
Column
Interconnect
Row
Interconnect
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K30EFI324-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K30EFI324-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K30EQC208-1 功能描述:IC APEX 20KE FPGA 300K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:APEX-20K® 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
EP20K30EQC208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K30EQC208-2 制造商:Rochester Electronics LLC 功能描述:- Bulk