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| 型號(hào)： | EP20K200EQC240-2ES |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁(yè)數(shù)： | 18/114頁(yè) |
| 文件大小： | 1623K |
| 代理商： | EP20K200EQC240-2ES |
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Copyright
2001 Altera Corporation. All rights reserved. AMMP, Altera, APEX, APEX 20K, APEX 20KE,
ByteBlaster, ClockBoost, ClockLock, ClockShift, EP20K30E, EP20K60E, EP20K100, EP20K100E, EP20K160E,
EP20K200, EP20K200E, EP20K300, EP20K400, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E, FastTrack,
FineLine BGA, MasterBlaster, MegaCore, MegaLAB, MultiCore, MultiVolt, NativeLink, Quartus, Quartus II,
SignalTap and Turbo Bit are trademarks and/or service marks of Altera Corporation in the United States and
other countries. Altera acknowledges the trademarks of other organizations for their respective products or
services mentioned in this document. Altera products are protected under numerous U.S. and foreign patents
and pending applications, maskwork rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s
standard warranty, but reserves the right to make changes to any products and services at
any time without notice. Altera assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to
obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
(408) 544-7104
Literature Services:
lit_req@altera.com
APEX 20K Programmable Logic Device Family Data Sheet
114
Altera Corporation
Printed on Recycled Paper.
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Updated Tables 114 and 115.
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Updated Timing Model section.
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Added Figure 37.
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Updated Figure 40.
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Updated Power Sequencing & Hot Socketing section.
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Updated Table 8.
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Included minor text changes.
Version 3.6 Changes
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Updated Figures 27 and 28.
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Updated Table 9.
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Included minor text changes.
Version 3.5 Changes
All preliminary information headings were removed from version 3.5.
Version 3.4 Changes
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K200EQC240-3ES | FPGA |
| EP20K200EQI208-1 | FPGA |
| EP20K200EQI208-1ES | FPGA |
| EP20K200EQI208-1X | FPGA |
| EP20K200EQI208-2 | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K200EQC240-2N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 832 Macro 168 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K200EQC240-2X | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 832 Macro 168 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K200EQC240-3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 832 Macro 168 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K200EQC240-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K200EQC240-3N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 832 Macro 168 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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