Table 57. EP20K60E fMAX
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP20K160ETC144-1
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 104/117闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC APEX 20KE FPGA 160K 144-TQFP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� APEX-20K®
LAB/CLB鏁�(sh霉)锛� 640
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 6400
RAM 浣嶇附瑷堬細 81920
杓稿叆/杓稿嚭鏁�(sh霉)锛� 88
闁€鏁�(sh霉)锛� 404000
闆绘簮闆诲锛� 1.71 V ~ 1.89 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 144-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-TQFP锛�20x20锛�
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Altera Corporation
87
APEX 20K Programmable Logic Device Family Data Sheet
Table 57. EP20K60E fMAX Routing Delays
Symbol
-1
-2
-3
Unit
Min
Max
Min
Max
Min
Max
tF1-4
0.24
0.26
0.30
ns
tF5-20
1.45
1.58
1.79
ns
tF20+
1.96
2.14
2.45
ns
Table 58. EP20K60E Minimum Pulse Width Timing Parameters
Symbol
-1
-2
-3
Unit
Min
Max
Min
Max
Min
Max
tCH
2.00
2.50
2.75
ns
tCL
2.00
2.50
2.75
ns
tCLRP
0.20
0.28
0.41
ns
tPREP
0.20
0.28
0.41
ns
tESBCH
2.00
2.50
2.75
ns
tESBCL
2.00
2.50
2.75
ns
tESBWP
1.29
1.80
2.66
ns
tESBRP
1.04
1.45
2.14
ns
Table 59. EP20K60E External Timing Parameters
Symbol
-1
-2
-3
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.03
2.12
2.23
ns
tINH
0.00
ns
tOUT C O
2.00
4.84
2.00
5.31
2.00
5.81
ns
tINSU PLL
1.12
1.15
-
ns
tINHP LL
0.00
-
ns
tOUT C OPLL
0.50
3.37
0.50
3.69
-
ns
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