參數(shù)資料
型號: EP20K1500EFI1020-2ES
英文描述: 5V, Byte Alterable E2PROM; Temperature Range: -40°C to 85°C; Package: 32-CerDIP
中文描述: FPGA的
文件頁數(shù): 40/114頁
文件大?。?/td> 1623K
代理商: EP20K1500EFI1020-2ES
Altera Corporation
31
APEX 20K Programmable Logic Device Family Data Sheet
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in Figure 19.
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
ESB
to System Logic
Address Decoder
Port A
Port B
address_a[]
address_b[]
data_a[]
data_b[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
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EP20K160EBC356-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 271 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256