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參數(shù)資料
| 型號： | EP20K100QI240-1ES |
| 英文描述： | 5-Channel Integrated LCD Supply; Temperature Range: -40°C to 85°C; Package: 40-QFN T&R |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 56/114頁 |
| 文件大小： | 1623K |
| 代理商： | EP20K100QI240-1ES |
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46
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
MultiVolt I/O
Interface
The APEX device architecture supports the MultiVolt I/O interface
feature, which allows APEX devices in all packages to interface with
systems of different supply voltages. The devices have one set of VCC pins
for internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
The APEX 20K VCCINT pins must always be connected to a 2.5 V power
supply. With a 2.5-V VCCINT level, input pins are 2.5-V and 3.3-V tolerant.
Certain devices, identified by a “V” suffix following the speed grade in the
ordering code (e.g., EP20K400BC652-1V), are 5.0-V tolerant. The VCCIO
pins can be connected to either a 2.5-V or 3.3-V power supply, depending
on the output requirements. When VCCIO pins are connected to a 2.5-V
power supply, the output levels are compatible with 2.5-V systems. When
the VCCIO pins are connected to a 3.3-V power supply, the output high is
3.3 V and is compatible with 3.3-V or 5.0-V systems.
Table 12 summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support.
Notes:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher
than VCCIO.
(2)
APEX 20K devices with a “V” suffix are 5.0-V tolerant.
(3)
When VCCIO = 3.3 V, an APEX 20K device can drive a 2.5-V device with 3.3-V
tolerant inputs.
Open-drain output pins on 5.0-V tolerant APEX 20K devices (with a pull-
up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that
require a VIH of 3.5 V. When the pin is inactive, the trace will be pulled up
to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state;
it will never drive high. The rise time is dependent on the value of the pull-
up resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor.
Table 12. 5.0-V Tolerant APEX 20K MultiVolt I/O Support
VCCIO (V)
Input Signals (V)
Output Signals (V)
2.5
3.3
5.0
2.5
3.3
5.0
2.5
vv(1)
v
3.3
vv
v(3)
vv
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K100QI240-2 | Field Programmable Gate Array (FPGA) |
| EP20K100QI240-2ES | FPGA |
| EP20K100QI240-3 | Field Programmable Gate Array (FPGA) |
| EP20K100QI240-3ES | Boost Regulator with Dual Feedback Paths and Output Disconnect for Passive OLED Power Applications; Temperature Range: -40°C to 85°C; Package: 10-DFN T&R |
| EP20K100RI208-1 | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K100QI240-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K100QI240-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100QI240-2V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K100QI240-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K100QI240-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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