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參數(shù)資料
| 型號(hào)： | EP20K100QI208-3ES |
| 英文描述： | 4-Channel Integrated LCD Supply with Dual VCOM Amplifiers; Temperature Range: -40°C to 85°C; Package: 48-QFN T&R |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 63/114頁 |
| 文件大?。?/td> | 1623K |
| 代理商： | EP20K100QI208-3ES |
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52
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 16 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
Notes:
(1)
To implement the ClockLock and ClockBoost circuitry with the Quartus II
software, designers must specify the input frequency. The Quartus II software
tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
fCLKDEV parameter specifies how much the incoming clock can differ from the
specified frequency during device operation. Simulation does not reflect this
parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock
period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured
before the rest of the device. If the incoming clock is supplied during configuration,
the ClockLock and ClockBoost circuitry locks during configuration because the
tLOCK value is less than the time required for configuration.
(4)
The tJITTER specification is measured under long-term observation.
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade
Devices
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
170
MHz
fCLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
170
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
80
MHz
fCLK4
Input clock frequency (ClockBoost
clock multiplication factor equals 4)
10
34
MHz
tOUTDUTY
Duty cycle for ClockLock/ClockBoost-
generated clock
40
60
%
fCLKDEV
Input deviation from user specification
in the Quartus II software (ClockBoost
clock multiplication factor equals one)
25,000
PPM
tR
Input rise time
5ns
tF
Input fall time
5ns
tLOCK
Time required for ClockLock/
ClockBoost to acquire lock
10
s
tSKEW
Skew delay between related
ClockLock/ ClockBoost-generated
clock
500
ps
tJITTER
Jitter on ClockLock/ ClockBoost-
generated clock (4)
200
ps
tINCLKSTB
Input clock stability (measured between
adjacent clocks)
50
ps
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K100QI240-1 | 5-Channel Integrated LCD Supply; Temperature Range: -40°C to 85°C; Package: 40-QFN |
| EP20K100QI240-1ES | 5-Channel Integrated LCD Supply; Temperature Range: -40°C to 85°C; Package: 40-QFN T&R |
| EP20K100QI240-2 | Field Programmable Gate Array (FPGA) |
| EP20K100QI240-2ES | FPGA |
| EP20K100QI240-3 | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K100QI240-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K100QI240-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100QI240-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K100QI240-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100QI240-2V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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