參數(shù)資料
型號： EP20K100QI208-2ES
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 65/114頁
文件大?。?/td> 1623K
代理商： EP20K100QI208-2ES
54
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(2)
The maximum lock time is 40 s or 2000 input clock cycles, whichever occurs first.
(3)
Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs are still
disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins
once the CLKLK_ENA pin goes high in user mode.
(4)
The PLL VCO operating range is 200 MHz fVCO 840 MHz for LVDS mode.
Table 18. APEX 20KE Clock Input & Output Parameters
Symbol
Parameter
I/O Standard
-1X Speed Grade
-2X Speed Grade
Units
Min
Max
Min
Max
fVCO (4)
Voltage controlled oscillator
operating range
200
500
200
500
MHz
fCLOCK0
Clock0
PLL output frequency
for internal use
1.5
335
1.5
200
MHz
fCLOCK1
Clock1
PLL output frequency
for internal use
20
335
20
200
MHz
fCLOCK0_EXT
Output clock frequency for
external clock0 output
3.3-V LVTTL
1.5
245
1.5
226
MHz
2.5-V LVTTL
1.5
234
1.5
221
MHz
1.8-V LVTTL
1.5
223
1.5
216
MHz
GTL+
1.5
205
1.5
193
MHz
SSTL-2 Class I
1.5
158
1.5
157
MHz
SSTL-2 Class II
1.5
142
1.5
142
MHz
SSTL-3 Class I
1.5
166
1.5
162
MHz
SSTL-3 Class II
1.5
149
1.5
146
MHz
LVDS
1.5
420
1.5
350
MHz
fCLOCK1_EXT
Output clock frequency for
external clock1 output
3.3-V LVTTL
20
245
20
226
MHz
2.5-V LVTTL
20
234
20
221
MHz
1.8-V LVTTL
20
223
20
216
MHz
GTL+
20
205
20
193
MHz
SSTL-2 Class I
20
158
20
157
MHz
SSTL-2 Class II
20
142
20
142
MHz
SSTL-3 Class I
20
166
20
162
MHz
SSTL-3 Class II
20
149
20
146
MHz
LVDS
20
420
20
350
MHz
fIN
Input clock frequency
3.3-V LVTTL
1.5
290
1.5
257
MHz
2.5-V LVTTL
1.5
281
1.5
250
MHz
1.8-V LVTTL
1.5
272
1.5
243
MHz
GTL+
1.5
303
1.5
261
MHz
SSTL-2 Class I
1.5
291
1.5
253
MHz
SSTL-2 Class II
1.5
291
1.5
253
MHz
SSTL-3 Class I
1.5
300
1.5
260
MHz
SSTL-3 Class II
1.5
300
1.5
260
MHz
LVDS
1.5
420
1.5
350
MHz
相關(guān)PDF資料
PDF描述
EP20K100QI208-3 4-Channel Integrated LCD Supply; Temperature Range: -25°C to 85°C; Package: 36-QFN T&R
EP20K100QI208-3ES 4-Channel Integrated LCD Supply with Dual VCOM Amplifiers; Temperature Range: -40°C to 85°C; Package: 48-QFN T&R
EP20K100QI240-1 5-Channel Integrated LCD Supply; Temperature Range: -40°C to 85°C; Package: 40-QFN
EP20K100QI240-1ES 5-Channel Integrated LCD Supply; Temperature Range: -40°C to 85°C; Package: 40-QFN T&R
EP20K100QI240-2 Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100QI208-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K100QI208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100QI240-1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K100QI240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100QI240-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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