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參數(shù)資料
| 型號(hào)： | EP20K100QC240-1 |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA） |
| 文件頁(yè)數(shù)： | 80/114頁(yè) |
| 文件大?。?/td> | 1623K |
| 代理商： | EP20K100QC240-1 |
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68
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
1
For DC Operating Specifications on APEX 20KE I/O standards,
please refer to Application Note 117 (Using Selectable I/O Standards
in Altera Devices).
Notes to tables:
(1)
See the Operating Requirements for Altera Devices Data Sheet.
(2)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6)
Typical values are for TA = 25° C, VCCINT = 1.8 V, and VCCIO = 1.8V, 2.5V or 3.3V.
(7)
These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 28 on
(8)
The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(9)
The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) This value is specified for normal device operation. The value may vary during power-up.
(12) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
(13) Capacitance is sample-tested only.
compliance on APEX 20K devices.
Table 34. APEX 20KE Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on dedicated
clock pin
VIN = 0 V, f = 1.0 MHz
12
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
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| EP20K100QC240-2ES | FPGA |
| EP20K100QC240-3 | Field Programmable Gate Array (FPGA) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K100QC240-1ES | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA |
| EP20K100QC240-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K100QC240-2ES | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA |
| EP20K100QC2403 | 制造商:Altera 功能描述:_ |
| EP20K100QC240-3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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