參數(shù)資料
型號(hào)： EP20K100ETI144-1ES
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 63/114頁
文件大?。?/td> 1623K
代理商： EP20K100ETI144-1ES
52
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 16 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
Notes:
(1)
To implement the ClockLock and ClockBoost circuitry with the Quartus II
software, designers must specify the input frequency. The Quartus II software
tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
fCLKDEV parameter specifies how much the incoming clock can differ from the
specified frequency during device operation. Simulation does not reflect this
parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock
period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured
before the rest of the device. If the incoming clock is supplied during configuration,
the ClockLock and ClockBoost circuitry locks during configuration because the
tLOCK value is less than the time required for configuration.
(4)
The tJITTER specification is measured under long-term observation.
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade
Devices
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
170
MHz
fCLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
170
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
80
MHz
fCLK4
Input clock frequency (ClockBoost
clock multiplication factor equals 4)
10
34
MHz
tOUTDUTY
Duty cycle for ClockLock/ClockBoost-
generated clock
40
60
%
fCLKDEV
Input deviation from user specification
in the Quartus II software (ClockBoost
clock multiplication factor equals one)
25,000
PPM
tR
Input rise time
5ns
tF
Input fall time
5ns
tLOCK
Time required for ClockLock/
ClockBoost to acquire lock
10
s
tSKEW
Skew delay between related
ClockLock/ ClockBoost-generated
clock
500
ps
tJITTER
Jitter on ClockLock/ ClockBoost-
generated clock (4)
200
ps
tINCLKSTB
Input clock stability (measured between
adjacent clocks)
50
ps
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