參數(shù)資料
型號： EP20K100ETC144-3ES
英文描述： 128-Tap DCP, 16kbit EEPROM, and I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 8-DFN
中文描述： FPGA的
文件頁數(shù)： 88/114頁
文件大小： 1623K
代理商： EP20K100ETC144-3ES
Altera Corporation
75
APEX 20K Programmable Logic Device Family Data Sheet
Figure 40. Synchronous Bidirectional Pin External Timing
Notes:
(1)
The output enable and input registers are LE registers in the LAB adjacent to a bi-
directional row pin. The output enable register is set with “Output Enable Routing=
Signal-Pin” option in the Quartus II software.
(2)
The LAB adjacent input register is set with “Decrease Input Delay to Internal Cells=
Off”. This maintains a zero hold time for lab adjacent registers while giving a fast,
position independent setup time. A faster setup time with zero hold time is possible
by setting “Decrease Input Delay to Internal Cells= ON” and moving the input
register farther away from the bi-directional pin. The exact position where zero
hold occurs with the minimum setup time, varies with device density and speed
grade.
Table 35 describes the fMAX timing parameters shown in Figure 36.
PRN
CLRN
DQ
PRN
CLRN
DQ
(1)
IOE Register
Bidirectional Pin
Dedicated
Clock
PRN
CLRN
DQ
(1)
XZBIDIR
t
ZXBIDIR
t
OUTCOBIDIR
t
INSUBIDIR
t
INHBIDIR
t
OE Register
Output IOE Register
Input Register
(2)
Table 35. APEX 20K fMAX Timing Parameters
(Part 1 of 2)
Symbol
Parameter
tSU
LE register setup time before clock
tH
LE register hold time after clock
tCO
LE register clock-to-output delay
tLUT
LUT delay for data-in
tESBRC
ESB Asynchronous read cycle time
tESBWC
ESB Asynchronous write cycle time
tESBWESU
ESB WE setup time before clock when using input register
tESBDATASU
ESB data setup time before clock when using input register
tESBADDRSU
ESB address setup time before clock when using input registers
tESBDATACO1
ESB clock-to-output delay when using output registers
tESBDATACO2
ESB clock-to-output delay without output registers
相關PDF資料
PDF描述
EP20K100ETI144-1ES FPGA
EP20K100FI324-3ES White LED Driver with PWM Dimming; Temperature Range: -40°C to 85°C; Package: 8-TDFN T&R
EP20K100QC208-1 White LED Driver with PWM Dimming; Temperature Range: -40°C to 85°C; Package: 8-TDFN T&R
EP20K100QC208-1ES White LED Driver with PWM Dimming; Temperature Range: -40°C to 85°C; Package: 8-TDFN T&R
EP20K100QC208-2 Field Programmable Gate Array (FPGA)
相關代理商/技術參數(shù)
參數(shù)描述
EP20K100ETI144-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ETI144-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ETI144-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100FC324-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100FC324-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*