參數(shù)資料
型號： EP20K100EFC144-1ES
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 62/114頁
文件大小： 1623K
代理商： EP20K100EFC144-1ES
Altera Corporation
51
APEX 20K Programmable Logic Device Family Data Sheet
Notes:
(1)
The PLL input frequency range for the EP20K100-1X device for 1x multiplication is
25 MHz to 175 MHz.
(2)
All input clock specifications must be met. The PLL may not lock onto an incoming
clock if the clock specifications are not met, creating an erroneous clock within the
device.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured
first. If the incoming clock is supplied during configuration, the ClockLock and
ClockBoost circuitry locks during configuration, because the lock time is less than
the configuration time.
(4)
The jitter specification is measured under long-term observation.
(5)
If the input clock stability is 100 ps, tJITTER is 250 ps.
tLOCK
Time required for
ClockLock/ClockBoost to acquire
lock(4)
10
s
tSKEW
Skew delay between related
ClockLock/ClockBoost-generated
clocks
500
ps
tJITTER
Jitter on ClockLock/ClockBoost-
generated clock (5)
200
ps
tINCLKSTB
Input clock stability (measured
between adjacent clocks)
50
ps
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade
Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100EFC144-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EFC144-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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