參數(shù)資料
型號： EP20K100EBI356-3ES
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 55/114頁
文件大?。?/td> 1623K
代理商： EP20K100EBI356-3ES
Altera Corporation
45
APEX 20K Programmable Logic Device Family Data Sheet
Figure 29. APEX 20KE I/O Banks
Notes:
(1)
The first two I/O pins that border the LVDS blocks can only be used for input to
maintain an acceptable noise level on the VCCIO plane.
(2)
If the LVDS input and output blocks are not used for LVDS, they can support all of
the I/O standards and can be used as input, output, or bidirectional pins with
VCCIO set to 3.3 V, 2.5 V, or 1.8 V.
Power Sequencing & Hot Socketing
Because APEX 20K and APEX 20KE devices can be used in a mixed-
voltage environment, they have been designed specifically to tolerate any
possible power-up sequence. Therefore, the VCCIO and VCCINT power
supplies may be powered in any order.
Signals can be driven into APEX 20K devices before and during power-up
without damaging the device. In addition, APEX 20K devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX 20K and APEX 20KE devices operate as
specified by the user.
Under hot socketing conditions, APEX 20KE devices will not sustain any
damage, but the I/O pins will drive out.
LVDS/LVPECL
Input
Block (2)
(1)
LVDS/LVPECL
Output
Block (2)
(1)
Regular I/O Blocks Support
s LVTTL
s LVCMOS
s 2.5 V
s 1.8 V
s 3.3 V PCI
s LVPECL
s HSTL Class I
s GTL+
s SSTL-2 Class I and II
s SSTL-3 Class I and II
s CTT
s AGP
Individual
Power Bus
I/O Bank 8
I/O Bank 1
I/O Bank 2
I/O Bank 3
I/O Bank 4
I/O Bank 5
I/O Bank 6
I/O Bank 7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100EFC144-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EFC144-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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