Altera Corporation
4–27
February 2005
Stratix GX Device Handbook, Volume 1
Stratix GX Architecture
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or
256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit
configuration is not available in the true dual-port mode. Mixed-width
configurations are also possible, allowing different read and write
configurations.
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
Table 4–4. M4K RAM Block Configurations (Simple Dual-Port)
Read Port
Write Port
4K 1
2K × 2
1K
° 4 512 ° 8 256 ° 16 128 ° 32 512 ° 9 256 ° 18 128 ° 36
4K
× 1
v
vvv
v
2K
× 2
v
vvv
v
1K
× 4
v
vvv
v
512
× 8
v
vvv
v
256
× 16
v
vvv
v
128
× 32
v
vvv
v
512
× 9
vv
v
256
× 18
vv
v
128
× 36
vv
v
Table 4–5. M4K RAM Block Configurations (True Dual-Port)
Port A
Port B
4K × 1
2K × 2
1K × 4
512 × 8
256 × 16
512 × 9
256 × 18
4K
× 1
vvvvv
2K
× 2
vvvvv
1K
× 4
vvvvv
512
× 8
vvvvv
256
× 16
vvvvv
512
× 9
vv
256
× 18
vv