2–20
Altera Corporation
Stratix Device Handbook, Volume 2
July 2005
Clock Modes
All registers shown have asynchronous clear ports, except when using
the M-RAM. M-RAM blocks have asynchronous clear ports on their
output registers only.
(1)
The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
(2)
For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
(3)
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
(4)
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
8
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
D
ENA
Q
wraddress[ ]
address[ ]
Memory Block
256 16
512 8
1,024 4
2,048 2
4,096 1
Data In
Read Address
Write Address
Write Enable
Read Enable
Data Out
outclken
inclken
wrclock
rdclock
wren
rden
8 LAB Row
Clocks
To MultiTrack
Interconnect
D
ENA
Q
byteena[ ]
Byte Enable
Write
Pulse
Generator