
Altera Corporation
2–87
July 2005
Stratix Device Handbook, Volume 1
Stratix Architecture
Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock
management features.
Figure 2–52 shows a diagram of the enhanced PLL.
Figure 2–52. Stratix Enhanced PLL
(1)
External feedback is available in PLLs 5 and 6.
(2)
This single-ended external output is available from the g0 counter for PLLs 11 and 12.
(3)
These four counters and external outputs are available in PLLs 5 and 6.
(4)
This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and
PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11
and 12.
/n
Charge
Pump
VCO
/g0
/g1
/g2
/e0
8
4
Global
Clocks
/e1
/e2
I/O Buffers (3)
/e3
Δt
Lock Detect
To I/O buffers or general
routing
INCLK0
INCLK1
FBIN
PFD
/g3
/l1
/l0
From Adjacent PLL
/m
Spread
Spectrum
I/O buffers (2)
(1)
Loop
Filter
& Filter
Programmable
Time Delay on
Each PLL Port
Post-Scale
Counters
Clock
Switch-Over
Circuitry
Phase Frequency
Detector
VCO Phase Selection
Selectable at Each
PLL Output Port
VCO Phase Selection
Affecting All Outputs
Δt
Regional
Clocks
4