You can configure Stratix
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1S20F672C6
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 689/864闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX FPGA 20K LE 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 20
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 1846
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 18460
RAM 浣嶇附瑷�(j矛)锛� 1669248
杓稿叆/杓稿嚭鏁�(sh霉)锛� 426
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
鍏跺畠鍚嶇ū锛� 544-1853
EP1S20F672C6-ND
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Altera Corporation
11鈥�1
July 2005
11. Configuring Stratix &
Stratix GX Devices
Introduction
You can configure Stratix and Stratix GX devices using one of several
configuration schemes. All configuration schemes use either a
microprocessor, configuration device, or a download cable. See
This chapter discusses how to configure one or more Stratix or Stratix GX
devices. It should be used together with the following documents:
鈻�
MasterBlaster Serial/USB Communications Cable Data Sheet
鈻�
USB Blaster USB Port Download Cable Development Tools Data Sheet
鈻�
ByteBlaster II Parallel Port Download Cable Data Sheet
鈻�
ByteBlasterMV Parallel Port Download Cable Data Sheets
鈻�
Configuration Devices for SRAM-Based LUT Devices Data Sheet
鈻�
Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet
Table 11鈥�1. Stratix & Stratix GX Device Configuration Schemes
Configuration Scheme
Typical Use
Fast passive parallel (FPP)
Configuration with a parallel synchronous configuration device or microprocessor
interface where eight bits of configuration data are loaded on every clock cycle.
Passive serial (PS)
Configuration with a serial synchronous microprocessor interface or the
MasterBlasterTM communications cable, USB Blaster, ByteBlasterTM II, or
ByteBlasterMV parallel port download cable.
Passive parallel
asynchronous (PPA)
Configuration with a parallel asynchronous microprocessor interface. In this
scheme, the microprocessor treats the target device as memory.
Remote/local update FPP
Configuration using a NiosTM (16-bit ISA) and Nios II (32-bit ISA) or other
embedded processor. Allows you to update the Stratix or Stratix GX device
configuration remotely using the FPP scheme to load data.
Remote/local update PS
Passive serial synchronous configuration using a Nios or other embedded
processor. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PS scheme to load data.
Remote/local update PPA
Passive parallel asynchronous configuration using a Nios or other embedded
processor. In this scheme, the Nios microprocessor treats the target device as
memory. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PPA scheme to load data.
Joint Test Action Group
(JTAG)
Configuration through the IEEE Std. 1149.1 JTAG pins. You can perform JTAG
configuration with either a download cable or an embedded device. Ability to use
SignalTap II Embedded Logic Analyzer.
S52013-3.2
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PDF鎻忚堪
EP2AGX45DF25I5 IC ARRIA II GX FPGA 45K 572FBGA
EP2AGX45DF25C4 IC ARRIA II GX FPGA 45K 572FBGA
RSC49DRAS-S734 CONN EDGECARD 98POS .100 R/A PCB
EP2AGX65DF29C6N IC ARRIA II GX FPGA 65K 780FBGA
RMC49DRAS-S734 CONN EDGECARD 98POS .100 R/A PCB
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鍙冩暩(sh霉)鎻忚堪
EP1S20F672C6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1846 LABs 426 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F672C7 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1846 LABs 426 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F672C7N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1846 LABs 426 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F672I7 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1846 LABs 426 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F672I7N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 1846 LABs 426 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256