Stratix
鍙冩暩璩囨枡
鍨嬭櫉锛� EP1S20F484C6N
寤犲晢锛� Altera
鏂囦欢闋佹暩锛� 331/864闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX FPGA 20K LE 484-FBGA
鐢㈠搧鍩硅〒妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 20
绯诲垪锛� Stratix®
LAB/CLB鏁革細 1846
閭忚集鍏冧欢/鍠厓鏁革細 18460
RAM 浣嶇附瑷堬細 1669248
杓稿叆/杓稿嚭鏁革細 361
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 484-FBGA锛�23x23锛�
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Altera Corporation
3鈥�1
June 2006
3. External Memory
Interfaces in Stratix &
Stratix GX Devices
Introduction
Stratix and Stratix GX devices support a broad range of external
memory interfaces such as double data rate (DDR) SDRAM, RLDRAM II,
quad data rate (QDR) SRAM, QDRII SRAM, zero bus turnaround (ZBT)
SRAM, and single data rate (SDR) SDRAM. The dedicated phase-shift
circuitry allows the Stratix and Stratix GX devices to interface at twice the
system clock speed with an external memory (up to 200 MHz/400 Mbps).
Typical I/O architectures transmit a single data word on each positive
clock edge and are limited to the associated clock speed using this
protocol. To achieve a 400-megabits per second (Mbps) transfer rate, a
SDR system requires a 400-MHz clock. Many new applications have
introduced a DDR I/O architecture as an alternative to SDR architectures.
While SDR architectures capture data on one edge of a clock, the DDR
architectures captures data on both the rising and falling edges of the
clock, doubling the throughput for a given clock frequency and
accelerating performance. For example, a 200-MHz clock can capture a
400-Mbps data stream, enhancing system performance and simplifying
board design.
Most current memory architectures use a DDR I/O interface. These DDR
memory standards cover a broad range of applications for embedded
processor systems, image processing, storage, communications, and
networking. This chapter describes the hardware features in Stratix and
Stratix GX devices that facilitate the high-speed memory interfacing for
each memory standard. It then briefly explains how each memory
standard uses the features of the Stratix and Stratix GX devices.
f
You can use this document with AN 329: ZBT SRAM Controller Reference
Design for Stratix & Stratix GX Devices, AN 342: Interfacing DDR SDRAM
with Stratix & Stratix GX Devices, and AN 349: QDR SRAM Controller
Reference Design for Stratix & Stratix GX Devices.
External
Memory
Standards
The following sections provide an overview on using the Stratix and
Stratix GX device external memory interfacing features.
DDR SDRAM
DDR SDRAM is a memory architecture that transmits and receives data
at twice the clock speed of traditional SDR architectures. These devices
transfer data on both the rising and falling edge of the clock signal.
S52008-3.3
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EP1S20F484C7 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix I 1846 LABs 361 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F484C7N 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix I 1846 LABs 361 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F484I6 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix I 1846 LABs 361 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F484I6N 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix I 1846 LABs 361 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S20F672C6 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix I 1846 LABs 426 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256