參數(shù)資料
型號(hào): EP1K10TI100-2N
廠商: Altera
文件頁(yè)數(shù): 13/86頁(yè)
文件大小: 0K
描述: IC ACEX 1K FPGA 10K 100-TQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 270
系列: ACEX-1K®
LAB/CLB數(shù): 72
邏輯元件/單元數(shù): 576
RAM 位總計(jì): 12288
輸入/輸出數(shù): 66
門(mén)數(shù): 56000
電源電壓: 2.375 V ~ 2.625 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
其它名稱: 544-2083
20
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
LE Operating Modes
The ACEX 1K LE can operate in the following four modes:
Normal mode
Arithmetic mode
Up/down counter mode
Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The Altera
software, in conjunction with parameterized functions such as LPM and
DesignWare functions, automatically chooses the appropriate mode for
common functions such as counters, adders, and multipliers. If required,
the designer can also create special-purpose functions that use a specific
LE operating mode for optimal performance.
The architecture provides a synchronous clock enable to the register in all
four modes. The Altera software can set DATA1 to enable the register
synchronously, providing easy implementation of fully synchronous
designs.
Figure 11 shows the ACEX 1K LE operating modes.
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