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參數(shù)資料
| 型號(hào)： | EM421M924VTB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16Mb ( 2Banks ) Synchronous DRAM |
| 中文描述： | 16兆（2Banks）同步DRAM |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 833K |
| 代理商： | EM421M924VTB |
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Rev.01
16Mb SDRAM
12/18
Current
state
Addr.
Write recovering
X
X
X
Action
Nop
→
Enter row active after t
DPL
Nop
→
Enter row active after t
DPL
Nop
→
Enter row active after t
DPL
Start read, Determine AP
New w rite, Determine AP
Notes
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
BA/CA/A10
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
→
Enter precharge after t
DPL
Nop
→
Enter precharge after t
DPL
Nop
→
Enter precharge after t
DPL
ILLEGAL
ILLEGAL
3
3
Remark
H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
/CS
H
L
L
L
L
/R
X
H
H
H
H
/C
X
H
H
L
L
/W
X
H
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
X
H
H
L
L
H
L
H
L
X
H
L
H
L
Command
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
8
Write recovering
with AP
3,8
3
BA/RA
BA, A10
X
Op-Code
X
X
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
→
Enter idle after t
RC
Nop
→
Enter idle after t
RC
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
ILLEGAL
ILLEGAL
3
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
L
L
X
H
H
H
H
H
L
L
X
H
L
H
L
X
H
H
L
H
L
H
L
X
X
X
X
X
X
H
L
X
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/ BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRIT
ACT/PRE/PALL/
REF/SELF/MRS
Refreshing
Mode Register
Accessing
X
ILLEGAL
L
L
X
X
Notes 1.
All entries assume that CKE w as active (High level) during the preceding clock cycle.
2.
If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode.
All input buffers except CKE w ill be disabled.
3.
Illegal to bank in specified states;
→
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.
4.
If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode.
All input buffers except CKE w ill be disabled.
5.
Illegal if t
RCD
is not satisfied.
6.
Illegal if t
RAS
is not satisfied.
7.
Must satisfy burst interrupt condition.
8.
Must satisfy bus contention, bus turn around, and/or w rite recovery requirements.
9.
Must mask preceding data w hich don't satisfy t
DPL
.
10.
Illegal if t
RRD
is not satisfied.
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