參數(shù)資料
型號: EKK8011
英文描述: Low-Voltage, Single Supply, SPST, High Performance Analog Switches; Temperature Range: -40°C to 85°C; Package: 8-SOIC T&R
中文描述: 的USB PS / 2鍵盤控制器
文件頁數(shù): 20/24頁
文件大小: 465K
代理商: EKK8011
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
_______________________________________________________________________________________
5
IIN
IINi +1
IINi
IOFFSET
dRi
1V
VINi
VINi +1
IOFFSET
IINi -
VINi
dRi
(VINi + 1 - VINi)
=
1V
(IINi + 1 - IINi)
Figure 1. Effective Differential Input Resistance/Offset Current
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. VDD = 13V, a 10F capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1F capacitor connected to
SS_SHDN, NDRV = open circuit, VFB = 3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Note 1:
All min/max limits for the PD interface are production tested at +85°C (extended grade)/+70°C (commercial grade). Limits
at +25°C and -40°C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25°C
and +85°C (extended grade)/+70°C (commercial grade). Limits at -40°C are guaranteed by design, unless otherwise
noted.
Note 2:
The input offset current is illustrated in Figure 1.
Note 3:
Effective differential input resistance is defined as the differential resistance between GND and VEE without any external
resistance.
Note 4:
Classification current is turned off whenever the IC is in power mode.
Note 5:
See Table 2 in the PD Classification Mode section. RDISC and RCL must be 100ppm or better.
Note 6:
See Thermal Dissipation section for details.
Note 7:
When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k
(±1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage.
Note 8:
When the VUVLO is below VTH, G, UVLO, the MAX5942_ sets the turn-on voltage threshold internally (VUVLO,ON).
Note 9:
An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY will not cause the
MAX5942A/MAX5942B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: PGOOD references to OUT while PGOOD references to VEE.
Note 11: Guaranteed by design.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
SS Source Current
ISSO
VSS_SHDN = V-
2.0
4.5
6.5
A
SS Sink Current
1mA
Peak Soft-Start Voltage Clamp
No external load
2.331
2.420
2.500
V
VSS_SHDN falling (Note 11)
0.25
0.37
0.41
Shutdown Threshold
VSS_SHDN rising (Note 11)
0.53
0.59
0.65
V
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