參數(shù)資料
型號： EFM32TG222F32
廠商： Energy Micro
文件頁數(shù)： 3/136頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 32KB FLASH 48LQFP
特色產(chǎn)品： EFM32 Tiny Gecko
標準包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TQFP
包裝： 標準包裝
其它名稱： 914-1029-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
100
www.energymicro.com
Bits
Name
Type
Function
[2]
SYSRESETREQ
WO
System reset request:
0 = no system reset request
1 = asserts a signal to the EFM32 Reset Managment Unit (RMU) to
request a reset.
This is intended to force a large system reset of all major components
except for debug.
This bit reads as 0.
[1]
VECTCLRACTIVE
WO
Reserved for Debug use. This bit reads as 0. When writing to the register
you must write 0 to this bit, otherwise behavior is Unpredictable.
[0]
VECTRESET
WO
Reserved for Debug use. This bit reads as 0. When writing to the register
you must write 0 to this bit, otherwise behavior is Unpredictable.
4.3.6.1 Binary point
The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in the Interrupt
Priority Registers into separate group priority and subpriority fields. Table 4.18 (p. 100) shows how
the PRIGROUP value controls this split.
Table 4.18. Priority grouping
Interrupt priority level value, PRI_N[7:0]
Number of
PRIGROUP
Binary point
1
Group priority bits
Subpriority bits
Group priorities
Subpriorities
b100-b000
bxxx.00000
[7:5]
None
8
1
b101
bxx.y00000
[7:6]
[5]
4
2
b110
bx.yy00000
[7]
[6:5]
2
4
b111
b.yyy00000
None
[7:5]
1
8
1PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.
Note
Determining preemption of an exception uses only the group priority field, see
4.3.7 System Control Register
The SCR controls features of entry to and exit from low power state. See the register summary in
Table 4.12 (p. 94) for its attributes. The bit assignments are:
31
4 3 2 1 0
Reserved
SLEEPDEEP
SLEEPONEXIT
Reserved
5
SEVONPEND
Table 4.19. SCR bit assignments
Bits
Name
Function
[31:5]
-
Reserved.
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