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參數(shù)資料
| 型號(hào)： | EFM32TG110F32 |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 10/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT 32KB FLASH 24-QFN |
| 特色產(chǎn)品： | EFM32 Tiny Gecko |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Tiny Gecko |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 32MHz |
| 連通性： | EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.8 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x12b，D/A 1x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 914-1033-6 |
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
107
www.energymicro.com
4.3.11.2 Bus Fault Status Register
The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are:
7 6 5 4 3 2 1 0
BFARVALID
Reserved
STKERR
UNSTKERR
IMPRECISERR
PRECISERR
IBUSERR
Table 4.27. BFSR bit assignments
Bits
Name
Function
[7]
BFARVALID
Bus Fault Address Register (BFAR) valid flag:
0 = value in BFAR is not a valid fault address
1 = BFAR holds a valid fault address.
The processor sets this bit to 1 after a bus fault where the address is known. Other faults can
set this bit to 0, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler
must set this bit to 0. This prevents problems if returning to a stacked active bus fault handler
whose BFAR value has been overwritten.
[6:5]
-
Reserved.
[4]
STKERR
Bus fault on stacking for exception entry:
0 = no stacking fault
1 = stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the values in the context area
on the stack might be incorrect. The processor does not write a fault address to the BFAR.
[3]
UNSTKERR
Bus fault on unstacking for a return from exception:
0 = no unstacking fault
1 = unstack for an exception return has caused one or more bus faults.
This fault is chained to the handler. This means that when the processor sets this bit to 1,
the original return stack is still present. The processor does not adjust the SP from the failing
return, does not performed a new save, and does not write a fault address to the BFAR.
[2]
IMPRECISERR
Imprecise data bus error:
0 = no imprecise data bus error
1 = a data bus error has occurred, but the return address in the stack frame is not related to the
instruction that caused the error.
When the processor sets this bit to 1, it does not write a fault address to the BFAR.
This is an asynchronous fault. Therefore, if it is detected when the priority of the current
process is higher than the bus fault priority, the bus fault becomes pending and becomes active
only when the processor returns from all higher priority processes. If a precise fault occurs
before the processor enters the handler for the imprecise bus fault, the handler detects both
IMPRECISERR set to 1 and one of the precise fault status bits set to 1.
[1]
PRECISERR
Precise data bus error:
0 = no precise data bus error
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