參數資料
型號: EFM32G842F128
廠商: Energy Micro
文件頁數: 74/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLASH 64LQFP
標準包裝: 1
系列: Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,LCD,POR,PWM,WDT
輸入/輸出數: 53
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數據轉換器: A/D 8x12b,D/A 2x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 標準包裝
其它名稱: 914-1028-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
42
www.energymicro.com
Figure 3.4. ROR #3
31
1 0
Carry
Flag
...
2
3
4
5
3.3.4.5 RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry
flag into bit[31] of the result. See Figure 3.5 (p. 42) .
When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS
, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 3.5. RRX
31 30
1
0
Carry
Flag
...
3.3.5 Address alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word, or
multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses
are always aligned.
The Cortex-M3 processor supports unaligned access only for the following instructions:
LDR, LDRT
LDRH, LDRHT
LDRSH, LDRSHT
STR, STRT
STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an unaligned access,
and therefore their accesses must be address aligned. For more information about usage faults see
Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might
not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses
are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the
Configuration and Control Register to trap all unaligned accesses, see Section 4.3.8 (p. 101) .
3.3.6 PC#relative expressions
A PC#relative expression or label is a symbol that represents the address of an instruction or literal
data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler
calculates the required offset from the label and the address of the current instruction. If the offset is too
big, the assembler produces an error.
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