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參數(shù)資料
| 型號(hào)： | EDI7P016IDE2011C25 |
| 英文描述： | 2.5 Flash IDE drives(2.5閃速存儲(chǔ)器IDE器件（16MB）) |
| 中文描述： | 2.5閃存IDE驅(qū)動(dòng)器（2.5閃速存儲(chǔ)器的IDE器件（16MB的）） |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 63K |
| 代理商： | EDI7P016IDE2011C25 |
7PxxxIDE20xxC25
September 2000 Rev. 2 – ECO #13225
5
White Electronic Designs Corporation
(508) 366-5151
Drive Pin Explanation
Address bus (A0 to A2: input): In True IDE Mode only A [2 : 0] are used for selecting the one of eight
registers in the Task File.
Data bus (D0 to D15: input/output): Data bus is D0 to D15. D0 is the LSB of the Even Byte of the
Word. D8 is the LSB of the Odd Byte of the Word.
Card enable (-CE1, -CE2: input): In True IDE Mode -CE2 is used for select the Alternate Status
Register and the Device Control Register while -CE1 is the chip select for the other task file registers.
I/O read (-IORD: input): -IORD is used for control of read data in the Task File area.
I/O write (-IOWR: input): -IOWR is used for control of data write in the Task File area.
Interrupt request (IRQ: output): In True IDE Mode the signal is the active high Interrupt Request to the
host.
-IOIS16: (output) In True IDE Mode this output signal is asserted low when this device is expecting a
word data transfer cycle.
Disk active/slave present (-DASP: input/output): In True IDE Mode -DASP is the Disk Active/Slave
Present signal in the Master/Slave handshake protocol.
Reset (-RESET: input): By assertion of the RESET signal, all registers of this card are cleared and the
RDY/-BSY signal turns to high level. In True IDE Mode -RESET is the active low hardware reset from
the host.
Wait (-WAIT, IORDY: output):. In True IDE Mode this output signal may be used as IORDY. As for
this controller, this output is high impedance state constantly.
Pass diagnostic (-PDIAG: input/output):. In True IDE Mode, -PDIAG is the Pass Diagnostic signal in
the Master/Slave handshake protocol.
Card select (-CSEL: input): This internally pulled up signal is used to configure this device as a Master
or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as
a Master. When the pin is open, this device is configured as a Slave.
Master/Slave configuration: If the flash drive is being installed as a second drive (or Slave), pin 48 or pin
49 must be grounded. Pins 48 and 49 are inputs with pull up resistors and they are shorted internally. If
both pins are open, the flash drive is configured as the Master drive or as the only one drive in the system.
NOTE: Detailed description of flash drive functionality, including timing can be found in the technical
specification for PCMCIA card: ATA20 series .
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