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參數(shù)資料
| 型號(hào)： | EDD1232AABH-6B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | GT 2C 2#0 SKT PLUG |
| 中文描述： | 4M X 32 DDR DRAM, 0.7 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 621K |
| 代理商： | EDD1232AABH-6B-E |
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EDD1232AABH
Data Sheet E0533E50 (Ver. 5.0)
17
Current state
/CS
/RAS /CAS /WE
Address
Command
Operation
Next state
Read*
6
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
BST
Active
L
H
L
H
BA, CA, A8
READ/READA
Interrupting burst read
operation to
start new read
ILLEGAL*
13
Active
L
H
L
L
BA, CA, A8
WRIT/WRITA
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A8
PRE, PALL
Interrupting burst
read operation to
start pre-charge
Precharging
Read with auto-pre-
charge*
L
L
L
×
×
ILLEGAL
—
H
×
×
×
×
DESL
NOP
Precharging
L
H
H
H
×
NOP
NOP
Precharging
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A8
READ/READA
ILLEGAL*
14
—
L
H
L
L
BA, CA, A8
WRIT/WRITA
ILLEGAL*
14
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
—
L
L
H
L
BA, A8
PRE, PALL
ILLEGAL*
11, 14
—
L
L
L
×
×
ILLEGAL
—
Write*
8
H
×
×
×
×
DESL
NOP
Write
recovering
Write
recovering
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A8
READ/READA
Interrupting burst write
operation to
start read operation.
Interrupting burst write
operation to
start new write
operation.
ILLEGAL*
11
Read/ReadA
L
H
L
L
BA, CA, A8
WRIT/WRITA
Write/WriteA
L
L
H
H
BA, RA
ACT
—
L
L
H
L
BA, A8
PRE, PALL
Interrupting write
operation to start pre-
charge.
Idle
L
L
L
×
×
ILLEGAL
—
Write recovering*
9
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A8
READ/READA
Starting read operation. Read/ReadA
L
H
L
L
BA, CA, A8
WRIT/WRITA
Starting new write
operation.
ILLEGAL*
11
Write/WriteA
L
L
H
H
BA, RA
ACT
—
L
L
H
L
BA, A8
PRE/PALL
ILLEGAL*
11
—
L
L
L
×
×
ILLEGAL
—
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD1232AAFA | 128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AAFA-6B-E | 128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AAFA-7A-E | 128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AABH-7A-E | GT 3C 3#16S PIN PLUG |
| EDD1232ABBH | 128M bits DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD1232AABH-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AAFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AAFA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AAFA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232ABBH | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
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