參數(shù)資料
型號(hào): EBD52UC8AKDA
廠商: Elpida Memory, Inc.
英文描述: 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)
中文描述: 蘇512MB的DDR SDRAM的內(nèi)存(6400字× 64位,2個(gè)等級(jí))
文件頁數(shù): 11/19頁
文件大?。?/td> 199K
代理商: EBD52UC8AKDA
EBD52UC8AKDA
Preliminary Data Sheet E0367E20 (Ver. 2.0)
11
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current (ACTV-PRE)
IDD0
-6B
-7A, -7B
1320
1200
mA
CKE
VIH,
tRC = tRC (min.)
CKE
VIH, BL = 4,
CL = 2.5,
tRC = tRC (min.)
1, 2, 9
Operating current
(ACTV-READ-PRE)
IDD1
-6B
-7A, -7B
1560
1440
mA
1, 2, 5
Idle power down standby current
IDD2P
48
mA
CKE
VIL
4
Floating idle standby current
IDD2F
-6B
-7A, -7B
-6B
-7A, -7B
560
480
480
400
mA
VIH, /CS
VIH,
CKE
VIH, /CS
VIH,
CKE
Quiet idle standby current
IDD2Q
mA
Active power down
standby current
IDD3P
320
mA
CKE
VIL
3
Active standby current
IDD3N
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
880
800
2080
1840
2080
1840
3200
2800
mA
CKE
VIH, /CS
VIH
tRAS = tRAS (max.)
CKE
VIH, BL = 2,
CL = 2.5
CKE
VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input
VIL or
VIH
Input
VDD – 0.2 V
Input
0.2 V
3, 5, 6
Operating current
(Burst read operation)
Operating current
(Burst write operation)
IDD4R
mA
1, 2, 5, 6
IDD4W
mA
1, 2, 5, 6
Auto refresh current
IDD5
mA
Self refresh current
IDD6
48
mA
Operating current
(4 banks interleaving)
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. Data/Data mask transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at
VIH or
VIL.
IDD7A
-6B
-7A, -7B
3240
2800
mA
BL = 4
5, 6, 7
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Notes
Input leakage current
ILI
32
μA
VDD
VIN
VSS
Output leakage current
ILO
–10
10
μA
VDD
VOUT
VSS
Output high current
IOH
–15.2
mA
VOUT = 1.95V
1
Output low current
IOL
15.2
mA
VOUT = 0.35V
1
Note: 1. DDR SDRAM component specification.
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