參數(shù)資料
型號: EBD51RC4AKFA-7B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: JT 55C 55#22D PIN PLUG
中文描述: 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝: LEAD FREE, DIMM-184
文件頁數(shù): 11/19頁
文件大?。?/td> 198K
代理商: EBD51RC4AKFA-7B-E
EBD51RC4AKFA
Data Sheet E0377E20 (Ver. 2.0)
11
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current (ACTV-PRE)
IDD0
-6B
-7A, -7B
-6B
-7A, -7B
2190
2010
2640
2370
mA
CKE
VIH,
tRC = tRC (min.)
CKE
VIH, BL = 4,
CL = 3.5, tRC = tRC (min.)
1, 2, 9
Operating current
(ACTV-READ-PRE)
IDD1
mA
1, 2, 5
Idle power down standby current IDD2P
444
mA
CKE
VIL
4
Floating idle standby current
IDD2F
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
840
750
750
714
750
714
1380
1290
3450
3090
3630
3270
3450
3360
mA
CKE
VIH, /CS
VIH,
DQ, DQS, DM = VREF
CKE
VIH, /CS
VIH,
DQ, DQS, DM = VREF
4, 5
Quiet idle standby current
IDD2Q
mA
4, 10
Active power down standby
current
IDD3P
mA
CKE
VIL
3
Active standby current
IDD3N
mA
CKE
VIH, /CS
VIH
tRAS = tRAS (max.)
CKE
VIH, BL = 2,
CL = 3.5
CKE
VIH, BL = 2,
CL = 3.5
tRFC = tRFC (min.),
Input
VIL or
VIH
Input
VDD – 0.2 V
Input
0.2 V
3, 5, 6
Operating current
(Burst read operation)
Operating current
(Burst write operation)
IDD4R
mA
1, 2, 5, 6
IDD4W
mA
1, 2, 5, 6
Auto refresh current
IDD5
mA
Self refresh current
IDD6
444
mA
Operating current
(4 banks interleaving)
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM and DQS transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at
VIH or
VIL.
IDD7A
-6B
-7A, -7B
6150
5250
mA
BL = 4
1, 5, 6, 7
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM component Specification)
Parameter
Symbol
min.
max.
Unit
Test condition
Notes
Input leakage current
ILI
–2
2
μA
VDD
VIN
VSS
Output leakage current
ILO
–5
5
μA
VDDQ
VOUT
VSS
Output high current
IOH
–15.2
mA
VOUT = 1.95V
Output low current
IOL
15.2
mA
VOUT = 0.35V
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