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參數(shù)資料
| 型號： | EBD11UD8ABFB |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 1GB Unbuffered DDR SDRAM DIMM |
| 中文描述： | 1GB的DDR SDRAM的內(nèi)存緩沖 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 208K |
| 代理商： | EBD11UD8ABFB |
EBD11UD8ABFB
Preliminary Data Sheet E0296E20 (Ver. 2.0)
12
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Device Specification)
-6B
-7A
-7B
Parameter
Symbol
min.
max.
min.
max
min.
max
Unit Notes
Clock cycle time
(CL = 2)
tCK
7.5
12
7.5
12
10
12
ns
10
(CL = 2.5)
tCK
6
12
7.5
12
7.5
12
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min
(tCH, tCL)
—
min
(tCH, tCL)
—
min
(tCH, tCL)
—
tCK
DQ output access time from
CK, /CK
DQS output access time
from CK, /CK
DQS to DQ skew
tAC
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
2, 11
tDQSCK –0.6
0.6
–0.75
0.75
–0.75
0.75
ns
2, 11
tDQSQ
—
0.45
—
0.5
—
0.5
ns
3
DQ/DQS output hold time
from DQS
tQH
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
—
0.55
—
0.75
—
0.75
ns
Data-out high-impedance
time from CK, /CK
Data-out low-impedance
time from CK, /CK
tHZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
5, 11
tLZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
6, 11
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time tDS
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input hold time tDH
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input pulse
width
tDIPW
1.75
—
1.75
—
1.75
—
ns
7
Write preamble setup time
tWPRES 0
—
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
9
Write command to first DQS
latching transition
DQS falling edge to CK
setup time
DQS falling edge hold time
from CK
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tDSS
0.2
—
0.2
—
0.2
—
tCK
tDSH
0.2
—
0.2
—
0.2
—
tCK
DQS input high pulse width tDQSH
0.35
—
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
0.35
—
tCK
Address and control input
setup time
Address and control input
hold time
Address and control input
pulse width
Mode register set command
cycle time
Active to Precharge
command period
Active to Active/Auto refresh
command period
tIS
0.75
—
0.9
—
0.9
—
ns
8
tIH
0.75
—
0.9
—
0.9
—
ns
8
tIPW
2.2
—
2.2
—
2.2
—
ns
7
tMRD
2
—
2
—
2
—
tCK
tRAS
42
120000
45
120000
45
120000
ns
tRC
60
—
67.5
—
67.5
—
ns
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| EBD11UD8ADDA-7B | 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EBD11UD8ABFB-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM |
| EBD11UD8ABFB-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM |
| EBD11UD8ABFB-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM |
| EBD11UD8ADDA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks) |
| EBD11UD8ADDA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks) |
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