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| 型號： | EA-XPR-001 |
| 廠商： | Embedded Artists |
| 文件頁數(shù)： | 22/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD LPCXPRESSO LPC1343 |
| 標準包裝： | 1 |
| 系列： | LPCXpresso |
| 類型： | MCU |
| 適用于相關產(chǎn)品： | EA-XPR-021，ARM Cortex-M3 |
| 所含物品： | 板，軟件 |
| 配用： | EA-XPR-021-ND - BOARD BASE LPCXPRESSO |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
29 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
There are three levels of Code Read Protection:
1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors can not be erased.
2. CRP2 disables access to chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to chip via
the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART.
7.19.5 Boot loader
The boot loader controls initial operation after reset and also provides the means to
program the flash memory. This could be initial programming of a blank device, erasure
and re-programming of a previously programmed device, or programming of the flash
memory by the application program in a running system.
The boot loader code is executed every time the part is reset or powered up. The loader
can either execute the ISP command handler or the user application code, or, on the
LPC1342/43, it can program the flash image via an attached MSC device through USB
(Windows operating system only). A LOW level during reset applied to the PIO0_1 pin is
considered as an external hardware request to start the ISP command handler or the USB
device enumeration. The state of PIO0_3 determines whether the UART or USB interface
will be used (LPC1342/43 only).
7.19.6 APB interface
The APB peripherals are located on one APB bus.
7.19.7 AHB-Lite
The AHB-Lite connects the instruction (I-code) and data (D-code) CPU buses of the ARM
Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.
7.19.8 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see Section 7.19.1).
7.19.9 Memory mapping control
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EA-XPR-002 | 功能描述:開發(fā)板和工具包 - ARM LPCXPRESSO LPC1114 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| EA-XPR-003 | 功能描述:開發(fā)板和工具包 - ARM LPCXPRESSO LPC1769 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| EA-XPR-005 | 功能描述:開發(fā)板和工具包 - ARM LPCXPRESSO BOARD LPC1227 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| EA-XPR-006 | 功能描述:開發(fā)板和工具包 - ARM LPCXPRESSO BOARD LPC11C24 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| EA-XPR-007 | 功能描述:開發(fā)板和工具包 - ARM LPCXPRESSO BOARD LPC11U14 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
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