參數(shù)資料
型號(hào)： DSPIC33FJ32GP202T-I/MM
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC28
封裝： 6 X 6 MM, 0.90 MM HEIGHT, LEAD FREE, PLASTIC, QFN-28
文件頁(yè)數(shù)： 20/42頁(yè)
文件大小： 3790K
代理商： DSPIC33FJ32GP202T-I/MM
2011 Microchip Technology Inc.
DS70290G-page 27
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit.
The range of an N-bit 2’s complement integer is
-2N-1 to 2N-1 - 1.
For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including ‘0’.
For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 - 21-N). For a 16-bit fraction, the Q15 data range is
-1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
product that has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or word
sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The
data
accumulator
consists
of
a
40-bit
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation
source
and
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
Six STATUS register bits have been provided to
support saturation and overflow:
OA: AccA overflowed into guard bits
OB: AccB overflowed into guard bits
SA: AccA saturated (bit 31 overflow and
saturation)
or
AccA overflowed into guard bits and saturated (bit
39 overflow and saturation)
SB: AccB saturated (bit 31 overflow and
saturation)
or
AccB overflowed into guard bits and saturated (bit
39 overflow and saturation)
OAB: Logical OR of OA and OB
SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic
warning
trap
when
set
and
the
corresponding Overflow Trap Flag Enable bits (OVATE,
OVBTE) in the INTCON1 register are set (refer to
user application to take immediate action, for example,
to correct system gain.
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