參數(shù)資料
型號： DSPIC33FJ12GP201-I/SO
廠商： Microchip Technology
文件頁數(shù)： 7/90頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 12K 18SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
特色產(chǎn)品： PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝： 42
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 12KB（12K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： AC164339-ND - MODULE SKT FOR PM3 28SOIC
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
2005 Microchip Technology Inc.
Preliminary
DS70155C-page 13
dsPIC33F
3.4
DSP Engine
The DSP engine consists of a high-speed, single-
cycle, 17-bit x 17-bit multiplier, a barrel shifter and a
40-bit adder/subtractor with two target accumulators,
round and saturation logic, all of which enable efficient
execution
of
computationally
intensive
DSP
algorithms. The 17-bit x 17-bit multiplier is also utilized
for MCU-based multiply instructions.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB
and NEG. This feature greatly simplifies basic
arithmetic operations on 32-bit or 40-bit data.
A block diagram of the DSP engine is shown in
3.4.1
17 x 17-BIT MULTIPLIER
The 17 x 17-bit multiplier is capable of signed or
unsigned operation. It can suitably scale its output to
support either 1.31 fractional (Q31) or 32-bit integer
results, thereby diminishing the need to manually
post-process multiplication results for fractional data.
3.4.2
40-BIT ACCUMULATORS
The data accumulators have a 40-bit adder/subtractor
with automatic sign extension logic. It can select one of
two accumulators (A or B) as its pre-accumulation
source and post-accumulation destination. For the ADD
and LAC instructions, the data to be accumulated or
loaded can be optionally scaled via the barrel shifter
prior to accumulation.
The adder/subtractor generates overflow status bits,
SA/SB and OA/OB, which are latched and reflected in
the Status register and can also optionally generate an
arithmetic error trap:
Overflow from bit 39. This is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39. This is a
recoverable overflow. This bit (OA/OB) is set
whenever all the guard bits are not identical to
each other.
3.4.3
SATURATION AND OVERFLOW
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above and the user-configured control bits to
determine when to saturate and to what value to
saturate (a 40-bit or a 32-bit value).
In addition to adder/subtractor saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator.
The rounding logic performs a conventional (biased) or
convergent (unbiased) data rounding function during
an accumulator write (store). The Round mode is user-
selectable. Rounding generates a 16-bit, 1.15 data
value, which is passed to the data space write
saturation logic. Data space write saturation ensures
that the data in the accumulator is written back
accurately even when rounding is performed. If
rounding is not indicated by the instruction, a truncated
1.15 data value is stored and the least significant word
is simply discarded.
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