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| 型號： | DSP56321VF200 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 60/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 200MHZ 196-BGA |
| 標準包裝： | 126 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-FBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Power Consumption Considerations
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
4-3
Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the VCC and GND circuits.
All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with
internal pull-up resistors (TRST, TMS, DE).
The following pins must be asserted during the power-up sequence: RESET and TRST. A stable EXTAL
signal should be supplied before deassertion of RESET. If the VCC reaches the required level before
EXTAL is stable or other “required RESET duration” conditions are met (see Table 2-7), the device
circuitry can be in an uninitialized state that may result in significant power consumption and heat-up.
Designs should minimize this condition to the shortest possible duration.
Ensure that during power-up, and throughout the DSP56321 operation, VCCQH is always higher or equal to
the VCCQL voltage level.
If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due
to synchronous operation of the devices.
The Port A data bus (D[0–23]), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to maintain the
last output value even when the internal signal is tri-stated. Typically, no pull-up or pull-down resistors
should be used with these signal lines. However, if the DSP is connected to a device that requires pull-up
resistors (such as an MPC8260), the recommended resistor value is 10 K
or less. If more than one DSP
must be connected in parallel to the other device, the pull-up resistor value requirement changes as
follows:
—2 DSPs = 5 K
(mask sets 0K91M and 1K91M)/7 K (mask set 0K93M) or less
—3 DSPs = 3 K
(mask sets 0K91M and 1K91M)/4 K (mask set 0K93M) or less
—4 DSPs = 2 K
(mask sets 0K91M and 1K91M)/3 K (mask set 0K93M) or less
—5 DSPs = 1.5 K
(mask sets 0K91M and 1K91M)/2 K (mask set 0K93M) or less
—6 DSPs = 1 K
(mask sets 0K91M and 1K91M)/1.5 K (mask set 0K93M) or less
Note:
Refer to EB610/D DSP56321/DSP56321T Power-Up Sequencing Guidelines for detailed information
about minimizing power consumption during startup.
4.3 Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption
are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is
charging and discharging the capacitances of the pins and internal nodes.
Current consumption is described by this formula:
Equation 3:
Where:
C
=
node/pin capacitance
V
=
voltage swing
f
=
frequency of node/pin toggle
Example 4-1. Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33
MHz), the current consumption is expressed in Equation 4.
IC
V
f
×
=
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| DSP56321VF240 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 240Mhz/480MMACS 240Mhz EFCOP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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