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參數資料
| 型號： | DS8023-RRX+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 17/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 28-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 應用： | 智能卡 |
| 接口： | 模擬 |
| 電源電壓： | 2.7 V ~ 6 V |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 配用： | DS8023-KIT-ND - EVALUATION KIT FOR DS8023 |
DS8023
Smart Card Interface
9
Maxim Integrated
When a card is inserted into the reader (if PRES is
active), the host microcontroller can begin an activation
sequence (start a card session) by pulling CMDVCC
low. The following events form an activation sequence
(Figure 3):
1) Host: CMDVCC is pulled low.
2) DS8023: The internal oscillator changes to high
frequency (t0).
3) DS8023: The voltage generator is started simulta-
neously (t1 = t0).
4) DS8023: Raise VCC from 0 to 5V, 3V, or 1.8V with
a controlled slope (t2 = t1 + 1.5
× T). T is 64 times
the internal oscillator period (approximately 25s).
5) DS8023: I/O, AUX1, and AUX2 are enabled
(t3 = t1 + 4T).
6) DS8023: The CLK signal is applied to the C3 con-
tact (t4).
7) DS8023: RST is enabled simulataneously (t5 = t4 =
t11 + 7T).
An alternate sequence allows the application to control
when the clock is applied to the card.
1) Host: Set RSTIN high.
2) Host: Set CMDVCC low.
3) Host: Set RSTIN low between t3 and t5; CLK will now
start.
4) DS8023: RST stays low until t5, then RST becomes
the copy of RSTIN.
5) DS8023: RSTIN has no further effect on CLK after t5.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK starts at t3 (minimum
200ns after the transition on I/O, see Figure 4); after t5,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform acti-
vation with RSTIN held permanently high.
ATR
CMDVCC
RST
RSTIN
CLK
VCC
I/O
I/OIN
t0 t1
t2
t3
t4
t5 = tACT
Figure 3. Activation Sequence Using RSTIN and CMDVCC
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