參數(shù)資料
型號(hào)： DS5000FP-16
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 18/22頁(yè)
文件大?。?/td> 0K
描述： IC MODULE MICRO 16MHZ FLATPACK
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 66
系列： DS500x
核心處理器： 8051
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類(lèi)型： SRAM
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 80-BQFP
包裝： 托盤(pán)
DS5000FP
5 of 22
PIN DESCRIPTION (continued)
PIN
NAME
FUNCTION
11, 9, 7, 5, 1,
79, 77, 75
P0.0–P0.7
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1.
It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data
bus. When used in this mode, it does not require pullups.
13, 14
VCC
Power Supply, +5V
16, 8, 18, 80,
76, 4, 6, 20, 24,
26, 28, 30, 33,
35, 37
BA14–
BA0
Byte-Wide Address Bus Bits 14–0. This 15-bit bus is combined with the
nonmultiplexed data bus (BD7–BD0) to access NV SRAM. Decoding is
performed on CE1 and CE2 . Read/write access is controlled by R/
W. BA14–BA0
connect directly to an 8k or 32k SRAM. If an 8k RAM is used, BA13 and BA14
are unconnected. Note: BA13 and BA14 are inverted from the true logical address.
BA14 is lithium backed.
71, 69, 67, 65,
61, 59, 57, 55
BD7–BD0
Byte-Wide Data Bus Bits 7–0. This 8-bit bidirectional bus is combined with the
nonmultiplexed address bus (BA14–BA0) to access NV SRAM. Decoding is
performed on CE1 and CE2 . Read/write access is controlled by R/
W. BD7–BD0
connect directly to an 8k or 32k SRAM, and optionally to a real-time clock.
10
R/
W
Read/Write (Active Low). This signal provides the write enable to the SRAMs
on the byte-wide bus. It is controlled by the memory map and partition. The
blocks selected as Program (ROM) is write protected.
74
CE1
Active-Low Chip Enable 1. This is the primary decoded chip enable for memory
access on the byte-wide bus. It connects to the chip enable input of one SRAM.
CE1
is lithium backed. It will remain in a logic high inactive state when VCC falls
below VLI.
78
CE2
Active-Low Chip Enable 2. This chip enable is provided to bank switch to a
second block of 32k bytes of nonvolatile data memory. It connects to the chip
enable input of one SRAM or one lithium-backed peripheral such a real-time
clock. CE2 is lithium backed. It will remain in a logic high inactive state when
VCC falls below VLI.
12
VCCO
VCC Output. This is switched between VCC and VLI by internal circuits based on
the level of VCC. When power is above the lithium input, power will be drawn
from VCC. The lithium cell remains isolated from a load. When VCC is below VLI,
the VCCO switches to the VLI source. VCCO is connected to the VCC pin of an
SRAM.
54
VLI
Lithium Voltage Input. Connect to a lithium cell greater than VLImin and no
greater than VLImax as shown in the electrical specifications. Nominal value is +3V.
2, 3, 22, 23, 32,
42, 43, 62, 63,
72
N.C.
No Connection. Do not connect.
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