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參數(shù)資料
| 型號(hào)： | DS4550E+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 9B 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 接口： | I²C，JTAG |
| 輸入/輸出數(shù)： | 9 |
| 中斷輸出： | 無(wú) |
| 頻率 - 時(shí)鐘： | 400kHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 包括： | EEPROM |
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Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see Figure 5) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses including when it is reading bits from
the slave.
Acknowledgement
(ACK
and
NACK):
An
Acknowledgement (ACK) or Not Acknowledge (NACK)
is always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read or
the slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 5) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8-bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave returns control of
the SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
DS4550
I2C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
____________________________________________________________________
15
Figure 5. I2C Timing Diagram
SDA
SCL
tHD:STA
tLOW
tHIGH
tR
tF
tBUF
tHD:DAT
tSU:DAT
REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
START
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS4550E+ | 功能描述:接口-I/O擴(kuò)展器 9-Bit I2C/JTAG NV GPIO RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| DS4550E+T&R | 制造商:Maxim Integrated Products 功能描述:I2C AND JTAG NONVOLATILE 9-BIT I/O 20TSSOP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC I/O EXPANDER I2C 9B 20TSSOP |
| DS4550E+T&R | 功能描述:接口-I/O擴(kuò)展器 9-Bit I2C/JTAG NV GPIO RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| DS456 | 制造商:Miyama Electric 功能描述: |
| DS4560 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:12V Hot-Plug Switch |
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