參數(shù)資料
型號: DS4100HW+
廠商: Maxim Integrated Products
文件頁數(shù): 5/7頁
文件大小: 0K
描述: IC OSC CLOCK 100MHZ 10LCCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
類型: 時鐘振蕩器
頻率: 100MHz
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 71mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LCCC 裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 10-LCCC
安裝類型: 表面貼裝
DS4100H
100MHz HCSL Clock Oscillator
_______________________________________________________________________________________
5
Pin Description
PIN
NAME
FUNCTION
1
OE
Output Enable. On-chip pullup resistor. If connected to logic-high or left open, the clock output is
enabled. If connected to logic-low, the output is three-stated.
2
RREF
Connect a 475
±1% resistor from RREF to ground.
3
GND
Ground
4
OUTP
Positive Clock Output. Requires a series resistor and a pulldown resistor.
5
OUTN
Negative Clock Output. Requires a series resistor and a pulldown resister.
6
VCC
+3.3V Supply Input. Device power can range from 3.135V to 3.465V.
7–10
N.C.
No Connection
EP
Exposed Paddle. Do not connect this pad or place exposed metal under the pad.
OUTPUT
BUFFER
RECEIVER
RS
Z0
CL
Z0 = 50
Ω, 35in LENGTH
RT
RT = 50
Ω
RS
OUTP
OUTN
RS = 0
Ω FOR TEST, 0 TO 33Ω TO MINIMIZE RINGING IN APPLICATION.
CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY.
OUTP
OUTN
Z0
CL
CL = 2pF
Figure 2. Typical Termination for HCSL Driver and Test Conditions
OE
OUTP
tPZH
tPZ
0.7 x VCC
0.3 x VCC
GND
OUTN
tPZL
Figure 3. HCSL Output Timing Diagram When OE is Enabled and Disabled
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