參數資料
| 型號： | DS3911T+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT I2C QUAD 14TDFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 100 |
| 位數： | 10 |
| 數據接口： | I²C，串行 |
| 轉換器數目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.74W |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 14-TDFN-EP（3x5） |
| 包裝： | 管件 |
| 輸出數目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
DS3911
Temperature-Controlled, Nonvolatile,
I2C Quad DAC
14
Maxim Integrated
bytes, after the last address counter position of FFh
is accessed, the address counter automatically wraps
back to the first location, 00h. Read operations can
continue indefinitely.
I2C LUT Lockout
Both the I2C port and the LUT controller have access to
the LUTs. To prevent bus/data contention, the LUT con-
troller goes into a wait state instead of accessing the LUT
if the I2C port is active. Register updates and memory
access are briefly described below.
Afteravoltageortemperatureconversioncompletes
or the TINDEX register is calculated, the results are
loaded into a shadow SRAM for the associated regis-
ter by a backdoor that is not seen by the I2C port. The
value is pushed forward to the SRAM cell seen by the
I2C port at a later state. It is not pushed if the I2C port
is active.
AfterTINDEX is calculated and loaded into the shad-
ow SRAM, the LUT controller goes into a round-robin
loop where it updates the VCC VALUE, TEMP VALUE,
and TINDEX registers, reads the DAC OFFSET and
DAC LUT, performs the calculation, and loads the
result into the DAC VALUE register. This process is
where contention could occur. As such, the state
machine waits until I2C is inactive before performing
this process. If the I2C port were to become active
for a long time period, the temperature compensation
does not run.
Memory Description
The device’s internal memory consists of both volatile
and nonvolatile registers located in Lower Memory and
four separate memory tables (Upper Memory), as shown
in Figure 8.
The Lower Memory is addressed from 00h–7Fh. Lower
Memory contains temperature reading, VCC reading,
status bits, control registers, table select bits, and all four
The Upper Memory consists of the following four memory
tables. The table select bits, TS[3:0], determine which
table is currently accessible through I2C at memory loca-
tion 80h–FFh.
Table 04h contains a nonvolatile temperature-indexed
DAC0 LUT and DAC0 OFFSET register designed to
hold the pulse-density modulation profile for DAC0.
Table 05h contains a nonvolatile temperature-indexed
DAC1 LUT and DAC1 OFFSET register designed to
hold the pulse-density modulation profile for DAC1.
Table 06h contains a nonvolatile temperature-indexed
DAC2 LUT and DAC2 OFFSET registers designed to
hold the pulse-density modulation profile for DAC2.
Table 07h contains a nonvolatile temperature-indexed
DAC3 LUT and DAC3 OFFSET registers designed to
hold the pulse-density modulation profile for DAC3.
Shadowed EEPROM
The DAC POR memory locations are actually shadowed
EEPROM and are controlled by the shadowed EEPROM
bit, SEE. By default, SEE is not set and these locations
act as ordinary EEPROM. By setting SEE these locations
function like SRAM cells, which allow an infinite num-
ber of write cycles without concern of wearing out the
EEPROM. This also eliminates the requirement for the
EEPROM write time, tW. Because changes made with
SEE enabled do not affect the EEPROM, these changes
are not retained through power cycles. The power-on
value is the last value written with SEE disabled. This
function can be used to speed up calibration and mini-
mize the number of EEPROM write cycles.
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| DS3911T+ | 功能描述:ADC / DAC多通道 Fast APD Bias RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| DS3911T+T | 功能描述:ADC / DAC多通道 Fast APD Bias RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
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