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參數(shù)資料
| 型號(hào)： | DS3906U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 0K |
| 描述： | IC RESIST VAR TRPL 10USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 1.45k，2.54k，2.54k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 60 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
DS3906
Triple NV Low Step Size Variable
Resistor Plus Memory
12
____________________________________________________________________
Acknowledge Polling: Any time an EEPROM page is
written, the DS3906 requires the EEPROM write time
(tW) after the stop condition to write the contents of the
page to EEPROM. During the EEPROM write time, the
device does not acknowledge its slave address
because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the
DS3906, which allows communication to continue as
soon as the DS3906 is ready. The alternative to
acknowledge polling is to wait for a maximum period of
tW to elapse before attempting to access the device.
EEPROM Write Cycles: When EEPROM writes occur,
the DS3906 internally writes the whole EEPROM page (2-
bytes) even if only a single byte write was performed.
Writes that do not modify all 2 bytes on the page are
valid and do not corrupt any of other bytes on the same
page. Because the whole page is written, even bytes on
the page that were not modified during the transaction
are still subject to a write cycle. The DS3906’s EEPROM
write cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at the
worst-case temperature. It is capable of handling many
additional writes at room temperature.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read oper-
ation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a start condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a stop condition. However, since requiring the master
to keep track of the memory address counter is imprac-
tical, the following method should be used to perform
reads from a specified memory location.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a start condition, writes the slave address byte
(R/W =0), writes the memory address where it desires
to read, generates a repeated start condition, writes the
slave address byte (R/W = 1), reads data with ACK or
NACK as applicable, and generates a stop condition.
See Figure 3 for a read example using the repeated
start condition to specify the starting memory location.
Figure 3. I2C Communication Examples
SLAVE
ADDRESS*
START
1
0
1
0
A2
A1
A0
R/W
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MSB
LSB
MSB
LSB
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
READ/
WRITE
REGISTER/MEMORY ADDRESS
b7
b6
b5
b4
b3
b2
b1
b0
DATA
STOP
SINGLE BYTE WRITE
-WRITE RESISTOR 1
TO 00h
SINGLE BYTE WRITE
-WRITE FIRST BYTE OF
USER EEPROM TO FFh
SINGLE BYTE READ
-READ RESISTOR 0
TWO BYTE WRITE
-WRITE TWO BYTES OF
USER EEPROM TO 00h
START
STOP
1 0100000
00000 000
A0h
00h
START
REPEATED
START
A1h
MASTER
NACK
STOP
1 0100000
11111 000
F8h
10100 001
1 0100000
11111 001
A0h
F9h
STOP
RES 0
START 1 0100000
00000 000
A0h
00h
STOP
DATA
FFh
00h
EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND)
TYPICAL I2C WRITE TRANSACTION
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
00 000 000
1 1 111 111
A0h
00000000
TWO BYTE READ
-READ TWO BYTES OF
USER EEPROM
STARTING
FROM 00h
A)
C)
B)
D)
E)
START
STOP
101000 00
000 00000
A0h
00h
A1h
1010 0001
DATA
LOCATION 00h
DATA
LOCATION 01h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MASTER
ACK
MASTER
NACK
REPEATED
START
00000000
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