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參數(shù)資料
| 型號： | DS3902U-530+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 0K |
| 描述： | IC DIGITAL RESISTER EEPROM 8USOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 30k，50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 90-3902T+530 |
DS3902
Dual, NV, Variable Resistors
with User EEPROM
_____________________________________________________________________
7
ters in the Memory Map). The Configuration register
contains a bit (R0 and R1) for each resistor to enable
the High-Z state. When one of the High-Z bits is written
to a ‘1’, the corresponding resistor goes High-Z. When
written back to a ‘0’, the resistor goes back to the pro-
grammed resistance. Writing the Resistor 0 or Resistor
1 register to 00h, sets the respective resistor to its mini-
mum position (and minimum resistance). This value can
be found in the Analog Resistor Characteristics electri-
cal table. Writing Resistor 0 or Resistor 1 to FFh, sets
the resistor to its maximum resistance. The nominal
resistance (in ohms) of the resistors can be found in the
ordering information table at the beginning of this data
sheet.
When the DS3902 is powered up, the resistors are both
set to High-Z instantaneously while the settings stored
in EEPROM are recalled.
Slave Address & ADD_SEL Pin
The I2C slave address of the DS3902 depends on the
state of the ADD_SEL pin. If this pin is low, then the
slave address is A2h. If the ADD_SEL pin is high, then
the slave address is determined by the value stored in
EEPROM at address 00h. Refer to the Memory Map to
see the factory default of the slave address. The seven
most significant bits are used (the LSB is not used
because it is in the bit position of the R/W bit) to allow
the slave address to be programmed to one of 128
possible addresses. The I2C interface is described in
detail in a later section.
Software Write Protection
Software write protection is enabled by creating a two
byte password and writing it to the Password Setting
register (06h to 07h). When write protected, all memory
locations can be read, but only the Password Entry reg-
ister (04h to 05h) can be written. When the correct
password is entered, then the memory can be written
to. Refer to the Memory Map to see which registers can
be read/written with and without the password (PW).
When shipped from the factory, the password setting is
FFFFh. Likewise, every time the device is powered-up
the Password Entry register (which is RAM, not EEP-
ROM) defaults to FFFFh, giving full access to the
device. If write protection is not desired, then leave the
Password Setting at the factory default and ignore the
Password Entry register.
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START, and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Table 1. Memory Map
BINARY
ACCESS
DESCRIPTION
ADDR
MSB
LSB
FACTORY
DEFAULT
W/O PW
W/PW
TYPE
Slave Address
00h
SLAVE ADDRESS
X
A0h
R
R/W
EEPROM
Configuration
01h
XXXX
X
R1
R0
00h
R
R/W
EEPROM
Resistor 0
02h
b7
b6
b5
b4
b
b2
b1
b0
7Fh
R
R/W
EEPROM
Resistor 1
03h
b7
b6
b5
b4
b3
b2
b1
b0
7Fh
R
R/W
EEPROM
04h
PW MSB
FFh
Password
Entry
05h
PW LSB
FFh
W
RAM
06h
PW MSB
FFh
Password
Setting
07h
PW LSB
FFh
—
R/W
EEPROM
No
Memory
08h–
0Fh
——
—
User
Memory
10h–
1Fh
16 BYTES OF GENERAL PURPOSE EEPROM
ALL FFh
R
R/W
EEPROM
X = Don’t care.
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