DS3514
I2C Gamma and VCOM Buffer with EEPROM
10
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Block Diagram
LATCH B
LATCH A
MUX
10-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GHM
GHH
10 BITS
GM14 BANK A
GM14 BANK B
GM14 BANK C
GM14 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM14
GHH
GHM
GLM
GLL
GHM
LATCH B
LATCH A
MUX
10-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GHM
GHH
10 BITS
GM8 BANK A
GM8 BANK B
GM8 BANK C
GM8 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM8
LATCH B
LATCH A
MUX
10-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GLL
GLM
10 BITS
GM7 BANK A
GM7 BANK B
GM7 BANK C
GM7 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM7
GLM
GLL
LATCH B
LATCH A
MUX
10-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GLL
GLM
10 BITS
GM1 BANK A
GM1 BANK B
GM1 BANK C
GM1 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM1
LATCH B
LATCH A
MUX
8-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
VRL
VRH
8 BITS
VCOM BANK A
VCOM BANK B
VCOM BANK C
VCOM BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
VCOM
LOGIC
AND
CONTROL
MODE0 BIT (CR.0)
I2C
INTERFACE
I2C
COMPENSATION
COMP
MODE1 BIT (CR.1)
S0/S1 PINS
S0/S1 BITS (SOFT S0/S1)
LD
SDA
SCL
A0
S0
S1
LD
VCAP
VDD
VCC
GND
DS3514