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參數(shù)資料
| 型號： | DS3503U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/13頁 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL NV 128TAP 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 4 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
DS3503
NV, I2C, Stepper Potentiometer
8
_______________________________________________________________________________________
PERIOD/2 pulses have been applied to the SYNC
input. During this disable time, the power-up or new
WR value is applied to the RW potentiometer and
position 40h (code 64 decimal) is applied to the Y
potentiometer. Additionally, the step counter is
cleared during this disable time.
After the initialization pulses, stepping is enabled again.
The RW potentiometer starts from the power-up or new
WR value and the Y potentiometer starts from position
40h (code 64 decimal). The step counter starts from
zero in the up direction.
The stepping function is further described as follows:
An internal counter called PERIODCOUNT is set equal
to PERIOD.
The input to the RW potentiometer is WR + COUNT; the
input to the Y potentiometer is code 64 + COUNT.
When a SYNC pulse is received:
PERIODCOUNT = PERIODCOUNT - 1
If PERIODCOUNT = 0 (underflow), the following actions
occur:
If direction is UP:
COUNT = min (COUNT + 1, STEPCOUNT)
RW = min (127 - STEPCOUNT, WR + COUNT);
Y = 64 + COUNT
PERIODCOUNT is reset to PERIOD
If direction is DOWN:
COUNT = max (COUNT - 1, -STEPCOUNT)
RW = max (STEPCOUNT, WR - COUNT);
Y = 64 - COUNT
PERIODCOUNT is reset to PERIOD
If COUNT = STEPCOUNT, direction is changed from
UP to DOWN.
If COUNT = -STEPCOUNT, direction is changed from
DOWN to UP.
In this way the RW output steps up to WR+STEP-
COUNT, then steps down to WR-STEPCOUNT, and then
repeats the cycle. The outputs of the RW and Y DACs
change by one LSB = (VRH - VRL)/127 per PERIOD.
STEPCOUNT and PERIOD are programmable from I2C
and are stored in the nonvolatile SCR (Table 2).
The STEPCOUNT 5-bit value programmed into
SCR<4:0> controls the stepping range reflected in the
RW or Y outputs per Table 4, assuming STEPCOUNT <
IVR < 127 - STEPCOUNT:
Example 1:
WR = 41h (65 decimal): SCR<4:0> = STEPCOUNT
= 10000 (16 decimal)
RW range: 49
81 (decimal)
Y range: 48
80 (decimal)
Example 2:
WR = 50h (80 decimal): SCR<4:0> = STEPCOUNT
= 11000 (24 decimal)
RW range: 56
104 (decimal)
Y range: 40
88 (decimal)
Example 3: Clamping at Lower Rail
WR = 10h (16 decimal): SCR<4:0> = STEPCOUNT
= 11111 (31 decimal)
RW range: 0
62 (decimal)
Y range: 33
95 (decimal)
Example 4: Clamping at Upper Rail
WR = 70h (112 decimal): SCR<4:0> = STEPCOUNT
= 11111 (31 decimal)
RW range: 65
127 (decimal)
Y range: 33
95 (decimal)
SCR<4:0>
(BINARY)
DAC RANGE
0 0000
Stepping disabled; WR is
output
0 0001
Invalid setting. Do not
program.
0 0010
WR-2 to WR+2
0 0011
WR-3 to WR+3
0 0100
WR-4 to WR+4
0 0101
WR-5 to WR+5
. . .
1 1110
WR-30 to WR+30
. . .
1 1111
WR-31 to WR+31
Table 4. DAC Stepping Range
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