參數(shù)資料
型號(hào): DS33M30N+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/21頁(yè)
文件大小: 0K
描述: IC MAPPER ETHERNET 144CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
應(yīng)用: 數(shù)據(jù)傳輸
接口: SPI
電源電壓: 1.8V,2.5V,3.3V
封裝/外殼: 144-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 144-CSBGA(10x10)
包裝: 托盤
安裝類型: 表面貼裝
DS33M30/M31/M33 DATA SHEET
Rev: 010809
16 of 21
1.7.1 Ethernet MAC Interface
One E/FE/GbE port (MII/RMII/GMII)
10Mbps/100Mbps/1000Mbps data rates
Support for DTE or DCE operation
Half- and full-duplex flow control per IEEE 802.3
Jumbo frame lengths up to 10KB for GbE
64-byte minimum frame size
Ethernet management interface (MDIO)
Supports applicable RMON (RFC2819) counters
Promiscuous and broadcast discard modes
OAM frames can be intercepted, processed by host software, and responses inserted
1.7.2 Ethernet Bridging for 10/100
4K address and VLAN ID lookup table for learning and filtering
Programmable aging between one to 300 seconds in one-second intervals
1.7.3 Ethernet Traffic Classification
Ingress classification according to Ethernet COS
Programmable class map to four queues for each Ethernet port
1.7.4 Ethernet Traffic Profiling and Policing
Ingress classification by PCP or DSCP
Programmable class mapping to four queues
Programmable bandwidth profiling at either the port level or per-class level
Programmable bandwidth profiling for multicast and broadcast flows
Policing with programmable CIR/CBS
Nonconforming Ethernet frames discarded according to the configured BW profile
1.7.5 Ethernet Traffic Scheduling
Programmable scheduler for Ethernet flows toward PDH port(s):
o Strict priority, or
o Weighted queuing
1.7.6 Ethernet Control Frame Processing
Control frames, except PAUSE and OAM, are forwarded without processing
PAUSE and OAM frames can be programmed to be intercepted, discarded or forwarded
1.7.7 Q-in-Q
Programmable carrier VLAN tag insertion
1.8
SDRAM Interface
Interface for up to 256Mb DDR SDRAM (JEDEC JESD79D compliant)
Compatible with DDR266+
16-bit-wide data bus with dual edge transfers and auto refresh timing
SDRAM interface clock output of 125MHz
Direct connection to external DDR SDRAM
Example devices: Micron MT46V16M16, Samsung K4H561638F and Hynix HY5DU561622CF
1.9
Clock Rate Adapter (CLAD)
Creates DS3, E3, STS-1, and/or telecom bus clocks from single-input reference clock
Input reference clock to CLAD can be 77.76, 51.84, 44.736, 34.368, or 19.44MHz
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