參數(shù)資料
型號: DS32512DK
廠商: Maxim Integrated Products
文件頁數(shù): 81/130頁
文件大?。?/td> 0K
描述: KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計(jì)資源: DS32512 Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS32512
DS32506/DS32508/DS32512
54 of 130
Register Name:
GLOBAL.CR2
Register Description:
Global Control Register #2
Register Address:
004h
Bit #
15
14
13
12
11
10
9
8
Name
CLAD[6:0]
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
CLKD19
INTM
RAS
RAD
LSBCRE
GWRM
Default
0
Bits 14 to 8: CLAD I/O Mode (CLAD[6:0]).
These bits control the CLAD clock I/O pins REFCLK, CLKA, CLKB,
CLKC and CLKD. See Table 8-11 and Table 8-12 in Section 8.7.1.
Bit 5: CLKD Frequency is 19.44MHz (CLKD19).
This bit specifies the frequency to be output on CLKD when the
CLAD[3] configuration bit is high.
0 = 77.76MHz
1 = 19.44MHz
Bit 4: INT Pin Mode (INTM).
This bit determines the inactive mode of the INT pin. The INT pin always drives low
when an enabled interrupt source is active. See Section 8.10.
0 = Pin is high impedance when no enabled interrupts are active
1 = Pin drives high when no enabled interrupts are active
Bit 3: RDY/
ACK Select (RAS). This bit controls the microprocessor interface output pin RDY/ACK in Intel mode
(IFSEL = 100 or 110) and Motorola mode (IFSEL = 101 or 111).
0 = Normal operation: RDY in Intel mode and ACK in Motorola mode
1 = Reverse operation:
ACK in Intel mode and RDY in Motorola mode
Bit 2: RDY/
ACK Disable (RAD). This bit disables the microprocessor interface output pin RDY/ACK.
0 = Enable, normal operation
1 = Disable, tri-state
Bit 1: Latched Status Bit Clear-on-Read Enable (LSBCRE).
This bit determines when the latched status register
bits are cleared. See Section 8.8.5.
0 = Latched status register bits are cleared on a write
1 = Latched status register bits are cleared on a read
Bit 0: Global Write Mode (GWRM).
This bit enables the global write mode. When this bit is set, a write to a
register of any port causes a write to the same register in all the ports. In this mode register reads are not
supported and result in undefined data. See Section 8.8.6.
0 = Normal write mode
1 = Global write mode
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