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參數(shù)資料
| 型號(hào)： | DS3231MZ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大小： | 0K |
| 描述： | IC RTC I2C 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 類(lèi)型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，方波輸出 |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
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±5ppm, I2C Real-Time Clock
12
Maxim Integrated
DS3231M
to 00. The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals Sunday,
then 2 equals Monday, and so on). Illogical time and
date entries result in undefined operation. When reading
or writing the time and date registers, secondary buffers
are used to prevent errors when the internal registers
update. When reading the time and date registers, the
secondary buffers are synchronized to the internal reg-
isters on any I2C START and when the register pointer
rolls over to zero. The time information is read from these
secondary registers, while the clock continues to run.
This eliminates the need to reread the registers in case
the main registers update during a read. The countdown
chain is reset whenever the seconds register is writ-
ten. Write transfers occur on the acknowledge from the
device. Once the countdown chain is reset, to avoid roll-
over issues the remaining time and date registers must
be written within 1s.
Alarms
The device contains two time-of-day/date alarms. Alarm
1 can be set by writing to registers 07h–0Ah. Alarm
2 can be set by writing to registers 0Bh–0Dh. See
Table 2. The alarms can be programmed (by the alarm
enable and INTCN bits in the Control register) to acti-
vate the INT/SQW output on an alarm match condition.
Bit 7 of each of the time-of-day/date alarm registers are
mask bits (Table 2). When all the mask bits for each
alarm are logic 0, an alarm only occurs when the values
in the timekeeping registers match the corresponding
values stored in the time-of-day/date alarm registers.
The alarms can also be programmed to repeat every
second, minute, hour, day, or date. Table 3 shows the
possible settings. Configurations not listed in the table
result in illogical operation. The DY/DT bits (bit 6 of the
alarm day/date registers) control whether the alarm
value stored in bits 0–5 of that register reflects the day
of the week or the date of the month. If DY/DT is written
to logic 0, the alarm is the result of a match with date of
the month. If DY/DT is written to logic 1, the alarm is the
result of a match with day of the week. When the RTC
register values match alarm register settings, the cor-
responding alarm flag A1F or A2F bit is set to logic 1. If
the corresponding alarm interrupt enable A1IE or A2IE
bit is also set to logic 1, the alarm condition activates
the INT/SQW signal if the INTCN bit is set to logic 1. The
match is tested on the once-per-second update of the
time and date registers.
Table 3. Alarm Mask Bits
DY/DT
ALARM 1 REGISTER MASK BITS (BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
Alarm once a second
X
1
0
Alarm when seconds match
X
1
0
Alarm when minutes and seconds match
X
1
0
Alarm when hours, minutes, and seconds match
0
Alarm when date, hours, minutes, and seconds match
1
0
Alarm when day, hours, minutes, and seconds match
DY/DT
ALARM 2 REGISTER MASK BITS (BIT 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
Alarm once per minute (00 seconds of every minute)
X
1
0
Alarm when minutes match
X
1
0
Alarm when hours and minutes match
0
Alarm when date, hours, and minutes match
1
0
Alarm when day, hours, and minutes match
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